You-Sung Chang

Switch expansion architecture using local switching network

We propose a scheme for expanding switch modules to form a larger switch using the so-called local switching obtained by allowing bidirectional connection to the conventional three-stage Clos (1953) network switch. The performance of the proposed expansion architecture was compared to that of the conventional three-stage Clos network. We simulated 32/spl times/32 switching systems using two expansion architectures with the same switching strategy. Experiments show that the average switching latency is reduced by up to 60% in the expansion using the local switching network compared to one using the conventional three-stage Clos network switch. The latency reduction is dependent on the ratio of the delay of the switch fabric to that of the port controller. Expansion using the local switching network reduces latency across the switching system.

Conforming block inversion for low power memory

In this paper, we propose a scheme for reducing the power consumption of memory components by conforming memory contents to a precharging value. The scheme is oriented to application to single bitline structure of memory. It selectively stores normal or inverted data to reduce the number of bit accesses that have different values from the precharging value, which reduces overall bitline toggling and ultimately contributes to power reduction of the memory.

Customization of a CISC processor core for low-power applications

This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully utilizing the microcode-based control scheme, that is one of the most characterizing features of a CISC processor The optimization process includes two key techniques, generation of application-specific complex instructions (ASCI) and low-power-oriented microcode-ROM compilation, which independently operate at the two different levels of optimization. As a means of architectural level of optimization, application-specific complex instructions are generated so as to reduce the activities of fetch and decode units, and in the point of physical level of optimization, the microcode-ROM is compiled to reduce the bit-line toggling for each microcode-ROM access. Our experimental results based on transistor-level simulation show the proposed techniques can jointly reduce the total power consumption of the CISC processor core by up to 41%.