Bong-Il Park

A new single-clock flip-flop for half-swing clocking

We propose a new flip-flop configuration which saves about 60% of total clocking power using a half-swing clock. To use the half-swing clock, level converters or special clock drivers are traditionally required and the power consumptions of this logic cannot be ignored. In the proposed scheme, only NMOS devices are clocked with a half-swing clock in order to make it operate without the level converter or any other additional logics, and the random logic circuits except for the clock and flip-flops are supplied by V/sub cc/ while the clock network is supplied by V/sub cc//2. Compared to the conventional scheme, a great amount of power consumed in clocking which is responsible for a large portion of total chip power can be saved with the proposed new flip-flop configuration.

SCATOMi: scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture

FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multiFPGA system incorporating several state-of-the-art FPGAs. We propose a circuit partitioning algorithm called SCATOMi(scheduling driven algorithm for TOMi) for multiFPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(time-multiplexed, off-chip, multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures including mesh, crossbar and VirtualWire architecture.

Single cycle access cache for the misaligned data and instruction prefetch

In microprocessors, reducing the cache access time and the pipeline stall is critical to improve the system performance. To overcome the pipeline stall caused by the misaligned multi-words data or multi cycle accesses of prefetch codes which are placed over two cache lines, we proposed the Separated Word-line Decoding (SEWD) cache. SEWD cache makes it possible to access misaligned multiple words as well as aligned words in one clock cycle. This feature is invaluable in most microprocessors because the branch target address is usually misaligned, and many of data accesses are misaligned. 8K-byte SEWD cache chip consists of 489,000 transistors on a die size of 0.853/spl times/0.827 cm/sup 2/ and is implemented in 0.8 /spl mu/m DLM CMOS process operating at 60 MHz.

Synthesis and optimization of interface hardware between IP's operating at different clock frequencies

In system-on-a-chip design, interfacing of Intellectual Property (IP) blocks is one of the most important issues. Since most IPs are provided by different vendors, they have different interface schemes and different operating frequencies. In this paper, we propose a new interface synthesis method that enables one not only to handle the interface between IPs with different operating frequencies but also to minimize the hardware resource required for the interface. We have demonstrated the proposed algorithm by applying it to a real design example, MP3 decoder, and verified the IIS-to-PCI protocol converter on a real hardware system.

A regular layout structured multiplier based on weighted carry-save adders

A new parallel array multiplier based on a new circuit called a weighted carry-save adder (WCSA) is presented in this paper. Each row of the array consists of a (n+3) bit carry-save adder and one WCSA. Since the proposed WCSA enables the multiplier to be very regular as well as to have less operation complexity at the final addition stage than that of conventional implementations, the proposed WCSA is better suited for hardware implementation. Compared with the previous implementations, the proposed multiplier yields an area reduction of 21% for 64/spl times/64 multiplication. A 16/spl times/16 multiplier implemented in 0.8 /spl mu/m CMOS DLM technology functions at more than 60 MHz. The chip is 1.04/spl times/1.15 mm/sup 2/ with 7877 transistors.

SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine

This paper describes an interface controller called SmartGlue which enables a processor to interface with peripherals and makes a system reconfigurable by programming FPGA on the fly. By supporting standard interfaces and plug and play mechanism for the processor and FPGA, one can use any type of processors and FPGAs to implement a field programmable computing machine. The performance and utility of the SmartGlue was validated by applying its silicon implementation into a real system.

Interface synthesis for IP based design

In system-on-a-chip design, interfacing of Intellectual Property (IP) blocks is one of the most important issues. Since most IPs are provided by different vendors, they have different interface schemes and different operating frequencies. In this paper, we propose a new interface synthesis method that enables one not only to handle the interface between IPs with different operating frequencies but also to minimize the hardware resource required for the interface. We have demonstrated the proposed algorithm by applying it to a real design example, MP3 decoder, and verified the IIS-to-PCI protocol converter on a real hardware system.

Customization of a CISC processor core for low-power applications

This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully utilizing the microcode-based control scheme, that is one of the most characterizing features of a CISC processor The optimization process includes two key techniques, generation of application-specific complex instructions (ASCI) and low-power-oriented microcode-ROM compilation, which independently operate at the two different levels of optimization. As a means of architectural level of optimization, application-specific complex instructions are generated so as to reduce the activities of fetch and decode units, and in the point of physical level of optimization, the microcode-ROM is compiled to reduce the bit-line toggling for each microcode-ROM access. Our experimental results based on transistor-level simulation show the proposed techniques can jointly reduce the total power consumption of the CISC processor core by up to 41%.