Youichi Enomoto
NEC
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Publication
Featured researches published by Youichi Enomoto.
Superconductor Science and Technology | 1999
Shuichi Nagasawa; Haruhiro Hasegawa; Tatsunori Hashimoto; Hideo Suzuki; Kazunori Miyahara; Youichi Enomoto
We have designed a 16 kbit superconducting latching/SFQ hybrid (SLASH) RAM, which enables high-frequency clock operation up to 10 GHz. The 16 kbit SLASH RAM consists of four 4 × 4 matrix arrays of 256 bit RAM blocks, block decoders, latching block drivers, latching block senses, impedance matched lines and the powering circuits. The 256 bit RAM block is composed of a 16 × 16 matrix array of vortex transitional memory cells, latching drivers, SFQ NOR decoders and latching sense circuits. We have also designed and implemented an SFQ NOR decoder that is composed of magnetically coupled multi-input OR gates and RSFQ inverters.
Archive | 1996
Katsumi Suzuki; Youichi Enomoto; Shoji Tanaka
Archive | 2002
Hideo Suzuki; S. Nagasawa; Kazunori Miyahara; Youichi Enomoto
Archive | 2000
S. Nagasawa; Kazunori Miyahara; Youichi Enomoto
Archive | 1996
Katsumi Suzuki; Youichi Enomoto; Shoji Tanaka; Keiichi Yamaguchi; Arthur T. Murphy
Archive | 2000
Haruhiro Hasegawa; Kazunori Miyahara; Tatsunori Hashimoto; S. Nagasawa; Youichi Enomoto
Archive | 1996
Masahito Ban; Tsuyoshi Takenaka; Katsumi Suzuki; Youichi Enomoto
Archive | 1996
Yoshihiro Ishimaru; Yuuji Mizuno; Katsumi Suzuki; Youichi Enomoto; Shoji Tanaka
Archive | 1997
Katsumi Suzuki; Youichi Enomoto; Shoji Tanaka
Archive | 1996
Christian Neumann; Katsumi Suzuki; Youichi Enomoto; Shoji Tanaka
