Youmei Harada
Hiroshima University
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Publication
Featured researches published by Youmei Harada.
Operative Techniques in General Surgery | 2002
Takashi Morimoto; Youmei Harada; Tetsushi Koide; Hans Jürgen Mattausch
This paper proposes a digital algorithm for gray-scale/color image segmentation of real-time video signals and a cell-network-based implementation architecture in state-of-the-art CMOS technology. Through extrapolation of test-chip-data design in 0.35 /spl mu/m CMOS technology and simulation results we predict that about 50,000 /spl sim/ 100,000 pixels can be integrated on a chip in a 0.09 /spl mu/m CMOS technology, realizing very high-speed segmentation at about 300 /spl mu/sec per gray-scale/color image. Consequently real-time color-video segmentation will become possible in near future.
The Japan Society of Applied Physics | 2002
Takashi Morimoto; Youmei Harada; Tetsushi Koide; Hans Jürgen Mattausch
l.Introduction Image segmentation is the process by which the original natural image is partitioned into meaningful regions and is an important initial task for higher-level image processing such as object recognition or object tracking. Several image segmentation algorithms have been proposed [1,2]. However, due to their complexity, compact digital VLSI implementation is impossible. For previously proposed analog VLSI approaches [3,4] the scalability to future sub-100nm,low-voltage CMOS technologies is questionable. In this paper, we present a lowcomplexity digital algorithm, offering high-density VLSIimplementation, comparable for gray-scale and color motionpicture segmentation.
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | 2004
Osamu Kiriyama; Takashi Morimoto; Hidekazu Adachi; Youmei Harada; Tetsushi Koide; Hans Jürgen Mattausch
We present a low-power design for real-time digital image segmentation LSI. We design the CMOS test-chip in a 0.35 /spl mu/m 2-Poly 3-Metal CMOS technology, based on a boundary active only architecture. The design area for 41 /spl times/ 31 pixels is 51.1mm/sup 2/ and the integration density is 26.5pixel/mm/sup 2/. From the circuit simulations at 3.3V supply voltage and 10MHz clock frequency, we obtain a power dissipation of 21.8mW and an image segmentation time of 23/spl mu/sec.
Archive | 2003
Tetsushi Koide; Hans Jürgen Mattausch; Takashi Morimoto; Youmei Harada
IEE Proceedings - Circuits, Devices and Systems | 2005
Takashi Morimoto; Youmei Harada; Tetsushi Koide; Hans Jürgen Mattausch
Archive | 2004
Tetsushi Koide; Hans Jürgen Mattausch; Takashi Morimoto; Youmei Harada
Archive | 2005
Tetsushi Koide; Hans Jürgen Mattausch; Takashi Morimoto; Youmei Harada
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications | 2002
Tetsushi Koide; Takashi Morimoto; Youmei Harada; Hans Jürgen Mattausch
Archive | 2008
Tetsushi Koide; Hans Jürgen Mattausch; Takashi Morimoto; Youmei Harada
Archive | 2004
Hans Jürgen Mattausch; Youmei Harada; Tetsushi Koide; Takashi Morimoto