Hidekazu Adachi

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

A novel algorithm for object tracking of video pictures, based on image segmentation and pattern matching as well as its FPGA/ASIC implementation architecture are presented. With image segmentation, we can detect all objects in the images no matter whether they are moving or not. Using image segmentation results of successive frames, we exploit pattern matching in a simple object feature space for tracking of objects. The proposed algorithm can be applied to multiple moving and still objects even in the case of a moving camera. The FPGA/ASIC implementation architecture is verified to enable real-time tracking of up to 220 objects, when realized with modern FPGA hardware.

Object tracking in video pictures based on image segmentation and pattern matching

We propose a novel algorithm for object tracking in video pictures, based on image segmentation and pattern matching. With image segmentation, we can detect all objects in images, whether they are moving or not. Using the image segmentation results of successive frames, we exploit pattern matching in a simple feature space for tracking the objects. Consequently, the proposed algorithm can be applied to multiple moving and still objects, even in the case of a moving camera. We describe the algorithm in detail and perform simulation experiments on object tracking which verify the tracking algorithms efficiency. VLSI implementation of the proposed algorithm is possible.

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching

This paper presents a real-time multi-object tracking architecture based on image segmentation and object matching and its FPGA/ASIC implementation. With image segmentation, we can detect all objects in the image no matter whether they are moving or not. Using image segmentation results of successive frames, we exploit object matching in a simple object feature space for tracking of objects. For both real-time processing and compact implementation, we developed a novel image-scan based region-growing segmentation architecture, which efficiently utilizes high access-bandwidth embedded memories. The structure of image-scan processing element array is at the same time exploited for object feature extraction. Using simple object features, object matching can be realized for finding the most similar object in the previous image frame. The proposed architecture is realized with modern FPGA hardware and is verified to enable real-time tracking of up to 230 objects for QVGA-size video picture at 20MHz clock frequency

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture

This paper presents a boundary-scan-only (BSO) video segmentation architecture and its FPGA-based prototype system for 80 times 60 video images (30 fps). In the proposed BSO architecture, an input image is divided into a number of small image blocks. Then only image blocks, that have boundary pixels in the currently grown region, are processed with a block-sized pixel-parallel processing unit. This enables large-sized video segmentation with the compact processing unit, so that FPGA-based real-time video segmentation can be realized. We have developed an evaluation system for 80 times 60 real-time image segmentation with a standard FPGA device in 130 nm CMOS technology, and also evaluated its performance with video images. From this FPGA implementation result, QVGA-sized real-time image segmentation is expected to become possible with a state-of-the-art FPGA device in 90nm CMOS technology

A low-power video segmentation LSI with boundary-active-only architecture

We designed a cell-network-based video segmentation test-chip in 0.35/spl mu/m CMOS technology including a power reduction technique which activates only boundary cells of currently grown regions. The effectiveness of the proposed technique is confirmed by measurement results for a 41/spl times/33-sized cell-network, with 23/spl mu/sec segmentation time (avg.) and 45.8mW power-dissipation (avg.) at 10MHz clock frequency.

Image-Scan Video Segmentation Architecture and FPGA Implementation

Reserch Center for Nanodevices and Systems, Hiroshima University, 1-4-2, Kagamiyama, Higashi-Hiroshima, 739-8527, Japan Phone: +81-82-424-6265 Fax: +81-82-424-3499 e-mail: {koide, hjm}@sxsys.hiroshima-u.ac.jp

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation

This letter presents a boundary-active-only (BAO) power reduction technique for cell-network-based region-growing video segmentation. The key approach is an adaptive situation-dependent power switching of each network cell, namely only cells at the boundary of currently grown regions are activated, and all the other cells are kept in low-power stand-by mode. The effectiveness of the proposed technique is experimentally confirmed with CMOS test-chips having small-scale cell networks of up to 41 × 33 cells, where an average of only 1.7% of the cells remains active after application of the proposed approach. About 85% power reduction is thus achievable without sacrificing real-time processing.

Low-power design for real-time image segmentation LSI and compact digital CMOS implementation

We present a low-power design for real-time digital image segmentation LSI. We design the CMOS test-chip in a 0.35 /spl mu/m 2-Poly 3-Metal CMOS technology, based on a boundary active only architecture. The design area for 41 /spl times/ 31 pixels is 51.1mm/sup 2/ and the integration density is 26.5pixel/mm/sup 2/. From the circuit simulations at 3.3V supply voltage and 10MHz clock frequency, we obtain a power dissipation of 21.8mW and an image segmentation time of 23/spl mu/sec.