Young Bum Koh

Control of Etch Slope during Etching of Pt in Ar/Cl2/O2 Plasmas

Pt patterns of the 0.25 μm design rule were etched at 20°C using a magnetically enhanced reactive ion etcher. The main problem of this device integration process is the redeposition of the etch products onto the pattern sidewall, making it difficult to reduce the pattern size. In both cases using a photoresist mask and an oxide mask, the redeposits of the etch products onto the sidewall were reduced by the addition of Cl 2 to Ar, although the etch slope was lowered to 45°. Using the oxide mask, by adding O 2 to the Cl-containing gas, the etch slope was increased up to 70°, and the redeposits were removed by an HCl cleaning process.

Preparation and characterization of iridium oxide thin films grown by DC reactive sputtering

Iridium oxide ( IrO2) thin films were successfully grown by a DC magnetron reactive sputtering method. It was found that the crystalline nature and morphology of IrO2 films were strongly dependent on the oxygen partial pressure, total pressure and growth temperature. The growth of IrO2 is well explained by the generic curve for the total pressure as a function of O2 content. The films showed good barrier performance between Pt and poly-Si up to 750° C. A 40-nm-thick Ba0.5Sr0.5TiO3 film was grown by RF magnetron sputtering on the Pt/IrO2/poly-Si electrode. The leakage current density and dielectric constant of a Pt/Ba0.5Sr0.5TiO3/Pt capacitor on the IrO2/poly-Si electrode were comparable to those of the capacitor on a SiO2/Si substrate. However, an additional ohmic layer was required to prevent the formation of a SiO2 layer between the IrO2 and poly-Si.

Preparation and Electrical Properties of SrTiO3 Thin Films Deposited by Liquid Source Metal-Organic Chemical Vapor Deposition (MOCVD)

SrTiO 3 thin films with thicknesses ranging from 30 nm to 60 nm were grown on 6-inch-diameter, platinized Si wafers by liquid source metal-organic chemical vapor deposition (MOCVD). The crystalline quality and cation concentrations of the films are strongly dependent on the deposition temperature with optimum temperatures ranging from 500°C to 550°C. Semi-conformal deposition on submicron-sized storage node patterns is obtained but further improvements in conformality and reproducibility are required. The dielectric constant is about 210 irrespective of the film thickness and leakage current densities are sufficiently small for the dynamic random access memory (DRAM) applications. SiO 2 equivalent thickness (T ox ) of the 30-nm-thick STO film is 0.51 nm. The finding that the leakage current density and dielectric constant are independent of the film thickness can be explained by a fully depleted model of the STO film.

Correlation between gate oxide reliability and the profile of the trench top corner in Shallow Trench Isolation (STI)

In order to develop a Shallow Trench Isolation (STI) which does not have trench corner induced degradation of the gate oxide, its integrities were evaluated with rounded, non-rounded top corner, and an addition of CVD SiO/sub 2/ spacer. In the experiment, we found that the rounded and SiO/sub 2/ spacered STI showed the best result meaning no harmful influence of the corner to the gate oxide integrity. Also, etch-back processes of the filled CVD SiO/sub 2/ were modified to eliminate the degradation of the gate oxide by a stress concentration at top corner kinks.

Effect of SiO2 Film Deposition on the Ferroelectric Properties of a Pt/Pb(Zr, Ti)O3/Pt Capacitor

The degradation of the ferroelectric properties of a Pt/Pb(Zr, Ti)O3/Pt capacitor due to the back-end process of the ferroelectric random access memory (FRAM) device fabrication process is studied with particular reference to the interlayer dielectric (ILD) and its passivation. The SiO2 film for the ILD layer was deposited by two methods: electron cyclotron resonance chemical vapor deposition (ECR CVD) using SiH4/ N2O gas and atmospheric pressure thermal CVD using tetra ethyl ortho-silicate (TEOS) and O3 ( O3-TEOS CVD). The ECR CVD-SiO2 deposition at temperatures higher than 300° C severely damaged the ferroelectric properties of the Pt/Pb(Zr, Ti)O3/Pt capacitor. However, when the SiO2 film was deposited at temperatures lower than 250° C by ECR CVD, the nonvolatile remnant polarization of a capacitor with an area of 100×100 µ m2 was found to be about 10 µ C/cm2, which makes this a valuable ILD process for FRAM fabrication. The ferroelectric property degradation of the Pt/Pb(Zr, Ti)O3/Pt capacitor by the O3-TEOS SiO2 was less severe than that of the ECR CVD-SiO2. The ferroelectricity of the capacitors damaged by the SiO2 film deposition was recovered by post-annealing.

Design considerations for patterned wafer bonding

In patterned wafer bonding process, the debonded area occurring at bonding interface results from the poor wafer flatness of patterned wafer or from the different bonding speed in each position of the wafer. By reducing pressure when bonding occurs and by using interlayer films, we observed that the bondability of the patterned wafers enhances. In such a case, the result was also experimentally proved to be effective for the suppression of particles. In order to obtain the accurate alignment of the bonded wafers we specially designed a vacuum bonding machine, which has a function of self-controlled alignment mechanism (Rotating angle of <0.01°, side margin of <100 µ m). Finally, we obtained void free thin silicon on insulator (SOI) device layer not affecting in the successive lithography process.

Characteristics of a Stabilized Pulsed Plasma via Suppression of Side-Band Modes

The instabilities caused by the reflected rf power in a pulsed-plasma operation employing modulated rf power was studied. By suppressing the side-band modes in the frequency domain, the pulsed plasma became more stable and produced less reflected power. The mode-suppressed pulsed plasma showed almost the same plasma characteristics as the conventional step-function-modulated pulsed plasma. The mode-suppressed plasma was applied to etch a polysilicon pattern. The etched polysilicon profile showed no charge-up defects, suggesting that the mode-suppressed plasma can be utilized for controlling the electron temperature in a more stable operation.

A NEW POST-TREATMENT FOR CHEMICAL-MECHANICAL POLISHING PROCESS OF VERY LARGE-SCALE INTEGRATED CIRCUIT TUNGSTEN VIAS

A method of cleaning silicon substrates after chemical-mechanical polishing (CMP) for the planarization of tungsten-plug patterned silicon wafers is discussed. A phosphoric acid solution with fluoroboric acid (PFM) is used for the post treatment process to replace the conventional scrubbing process. The optimum chemical composition for the new solution is found to be the mixing ratio of 1:50 (fluoroboric acid:phosphoric acid in volume) at a phosphoric acid concentration of 40 vol%. Its oxide selectivity over metals and particle removing power are good enough for the cleanup process after CMP. The contact resistance of vias treated by the PFM solution exhibits a good distribution compared to that of vias treated by conventional scrubbing. In conclusion, the PFM solution shows promising results as a post-treatment to W CMP of via contact formation.

Nitride cladded poly-Si spacer LOCOS (NCPSL) isolation technology for the 1 giga bit DRAM

A novel LOCOS type isolation technology, Nitride Cladded Poly-Si Spacer LOGOS (NCPSL) which is for the 1 giga bit DRAM, has been developed. The features of the NCPSL process are low birds beak encroachment and long effective isolation length, which are achieved by using substrate silicon recess etching, poly-Si sidewall spacer, and selectively deposited SiN to the poly-Si spacer. NCPSL isolation shows the excellent active definition, high punchthrough voltage, low junction leakage current, hump free transistor characteristic, and good gate oxide integrity. Considering its isolation characteristics, NCPSL is the very practical technology for the isolation of 1 giga bit DRAM.

The change of ferroelectric properties of Pt/Pb(Zr,Ti)O3/Pt capacitor due to SiO2 deposition

Abstract Degradation of ferroelectric properties of Pt/Pb(Zr,Ti)O3/Pt capacitor by the back-end process of ferroelectric random access memory (FRAM) device fabrication process was studied, particularly by the interlayer dielectric (ILD). The influence of ILD layer on the ferroelectric properties of Pt/Pb(Zr,Ti)O3/Pt capacitor was investigated. The SiO2 film for ILD layer was deposited by two methods; electron cyclotron resonance chemical vapor deposition (ECR CVD) using SiH4/N2O gas and atmospheric pressure thermal CVD using tetra ethyl ortho-silicate (TEOS) and O3(O3-TEOS CVD). The SiO2 deposition changed the ferroelectric properties of Pt/Pb(Zr,Ti)O3/Pt capacitor, varied according to the deposition condition and method. The degradation of ferroelectric property of Pt/Pb(Zr,Ti)O3/Pt capacitor by O3-TEOS SiO2 was less than that of ECR CVD-SiO2. However, both method could make the nonvolatile remanent polarization (NVPr) to be above 10 μC/cm2 at 5 V, which makes those processes valuable as ILD process of F...