Young-Han Kim

Analysis of bandwidth allocation strategies with access restrictions in broadband ISDN

Bandwidth allocation strategies with access restrictions for the integration of wideband (WB) and narrowband (NB) traffic in a broadband integrated services digital network (BISDN) are studied. Access restrictions are placed on both types of traffic to meet the grade of service required for each. The WB traffic is assumed nonqueuable, whereas the NB traffic may be queued. As an improved strategy, an access strategy which allows each type of traffic to use its bandwidth in the access-restricted region with the risk of being preempted by an arriving call for which the overflowed region is reserved is considered. Under this strategy, the preempted NB calls are queued at the head of a waiting room, and preempted WB calls are queued in another finite waiting room. The performance of these strategies is analyzed in terms of access delay for NB traffic and blocking probability for WB traffic by the matrix-geometric solution method. It is shown numerically that these strategies can easily be adapted to varying traffic loads by changing the restriction levels. >

A CMOS Transceiver for a Multistandard 13.56-MHz RFID Reader SoC

A CMOS transceiver for a multistandard 13.56-MHz radio-frequency identification reader system-on-a-chip (SoC) is designed and fabricated. The SoC consists of an RF/analog part for modulation/demodulation and a digital part for controlling the transceiver functionality. Prior to designing the integrated circuit, pre-experiments using discrete components and commercial tags are performed. With the results, overall functions and specifications are determined. For supporting multistandard, several blocks are designed with digital controls according to the standards. In the transmitter, a digitally controlled amplitude modulator for various modulation indexes and a power control circuit are adopted. In the receiver, a variable gain amplifier and a level-controllable comparator, which are also controlled digitally according to the standard, are introduced. The full transceiver SoC is implemented in the Chartered 0.18-¿m CMOS technology. The measurement results of the implemented chip indicate that the designed transceiver operates in a multistandard mode.

Fully integrated ultra-low-power passive UHF RFID transponder IC

This paper presents a low power UHF RFID tag IC with 512 bit Non volatile memory (NVM). The tag IC has −17 dBm minimum read operation power sensitivity. Analog function blocks, a digital baseband, and a memory system operate with 0.8 V ∼ 2.0 V supply voltage range without voltage regulator. Only current-starved ring oscillator operates 0.6 V with calibration. Most of analog blocks adopted low power subthreshold operating design. The memory system is chosen 512-bit Fowler-Nordheim tunneling NVM. Digital baseband is designed to clock gating, clock recovery, balanced power distribution, and adaptive power consumption methodology. The tag IC is implemented in the 0.18-μm CMOS technology. The overall power consumption of designed IC is only 2.64 μW at 0.8 V supply voltage. The chip size is 0.65 mm × 0.65 mm.

A 13.56MHz receiver SoC for multi-standard RFID reader

A HF (13.56 MHz) RFID receiver architecture SoC (System on Chip) is proposed. The receiver can be used in the standards of ISO/IEC 14443 type A/B, 15693, and 18000-3. Before designing the circuit, standard analysis is processed. And also, we did a previous measurement for preparing implementation as a chip level. That is, a RFID transceiver test board using commercial components was configured and tested. Through the board experiments, we checked the possibilities of operation of designed receiver. Based on the experiment results, the multi-standard 13.56 MHz RFID receiver SoC was designed and fabricated using TSMC 0.18 um CMOS technology. The test results show that designed receiver system as a chip level can be operated properly in multiple standard conditions.

An analog front-end for 13.56 MHz multi-standard RFID system

We analyzed 13.56 MHz RFID standards and obtained specifications of transmitting section and receiving section of the RFID reader. With these analyses, we proposed a multistandard 13.56 MHz RFID reader system. For supporting multistandard in 13.56 MHz RFID system, circuits for controlling modulation index and power emitted to the tag are added in transmitter. In order to accept to various response signal levels from the tag, a certain voltage is applied to the receiver after eliminating DC voltage at VGA input and internal reference voltage is set in comparator. From measurement using commercial tags and additional FPGA board, we can conclude that this transceiver chip is compatible with mentioned standards.

An ultra compact CMOS transceiver for HF multi-standard RFID reader

An ultra compact CMOS transceiver for HF multi-standard RFID application is proposed. For supporting multi-standard, two structures are adopted in a transmitter: ASK modulator with various modulation indexes and power control circuit which can control the recognition range between the reader and the tag. A receiver consists of a half-wave rectifier, an ASK demodulator using a supply-independent biasing circuit, and an adjustable Schmitt trigger. The designed transceiver is fabricated using TSMC 0.18 µm CMOS process. Through the simulation, the designed transceiver system can be operated in multiple standard conditions.

A fully integrated HF multi-standard RFID transceiver for compact mobile terminals

A fully integrated HF multi-standard RFID transceiver for compact mobile terminals is proposed. Considerations for multi-standard are concerned in each part of the proposed transceiver and all of them are implemented as digitally-controlled components. A transmitter controls its modulation index with a mode selector and its emitting power to tags with a power controller, thus covering various standards and recognition ranges. A receiver has a compact size as it excludes capacitors. In a receiver, an ASK demodulator controls its reference level of modulation by switching a resistor, and an adaptable Schmitt trigger alters its hysteresis range by switching additional transistors. The proposed transceiver is implemented in a TSMC 0.18 um CMOS technology. Measurement results of the transceiver and communication test between a reader with the transceiver and tags verify abilities of the proposed transceiver for multi-standard.