Young-hee Song

Thermal Characteristics of Chip Stack and Package Stack Memory Devices in the Component and Module Level

The demand of the high storage memory is providing a momentum for stacking technology in DRAM industry. As the stack technology is developed, more heat sources are embedded in the same package footprint and increase the device temperature. Therefore, the thermal management is one of most important issues in DRAM stack package. Since the chip stack and package stack technology are competing each other as a solution of DRAM stack, it is necessary to characterize thermal behavior of each package for better thermal management. Hence, in this paper, the authors studied the thermal performance characteristics of chip stack and package stack package in component and module level. The study is focused on the dual stack, which is most demanded stack height in DRAM market. The test package and module was assembled with the thermal test die and the DRAM junction temperature was measured to compare the thermal performance. The package stack package showed better thermal performance in component level because of its larger package size. On the other hand, the chip stack package showed better thermal performance in module level when the heat sink is used.

Development of Reliability Verification System for Robust Package Design

To achieve design for reliability (DFR), a reliability verification system (RVS) was developed. Package level and board level reliabilities were predicted by the developed system automatically and the design for six sigma (DFSS) was achieved. Process server and database server were developed. FEM mesh was generated automatically by well-organized builder, simulation conditions were assigned by standardized procedure, and reliabilities were calculated by developed life models. All data related to the simulation were managed by database system. High quality simulation was carried out easily and quickly. Robust package design was achieved by design optimization using the RVS.

High-performance Substrate Design for DRAM Flip-chip Interconnection using Etch-back Process

To apply an Au-stud bumping, which has the merit of being a supportable fine pad/bump pitch comparable to that of conventional wire-bonding, in the high-reliable, low-cost flip-chip packaging of high-speed DRAMs with a central dual-inline chip pad configuration, a new design method of the flip-chip package substrate was developed. In the method, a narrow, through-center plating line was formed between dual-in-line bump pads, all of which were connected to the central plating line. After thick electroplating of the bump pads for the reliable joint formation between an Au-stud bump and a package substrate, the central plating line was etched out. The Au-stud flip-chip substrate design method was applied to a 512 Mb GDDR4 DRAM, together with the PCB interconnect design to obtain balanced parasitics and improved power delivery, and the resulting 2-layer flip-chip package, showed improved performance, especially, at low supply voltage over the conventional 2-layer BOC package for the device.

Effect of surface conditions on interfacial adhesion between PCB and EMC

Adhesion strength of PCB and EMC interface was investigated. Surface conditions of PCB such as the number of plasma treatment, delay time before EMC molding, and moisture soak time were considered. Adhesion strength was measured by DCB test method. Energy release rate at each crack arresting position was measured. Fracture parameters were studied by numerical simulation. Surface of PCB was analyzed by water contact angle and FT-IR.

Characterization of Wire Bondability on Overhang Structured Chip in Multi Chip Package

Characteristics of wire bonding on the overhang structured chip were investigated in this study. During the wire bonding process, chip crack and bondability were severe factors for thin wafer bonding. Chip crack was investigated by chip strength test and parametric study was performed by changing bonding parameters, constant velocity, force, and power. Bondability was measured for 500, 700, and 1000 mum overhang length. Bonding strength was tested by ball shear test method. 700 mum overhang showed better performance than 500 mum. 1000 mum overhang showed very low bondability. Bonding characteristics were observed by numerical FEM method. Nonlinear dynamic analysis was performed. Unstable contact pressure and shear stress were observed between ball and metal pad. Noise of reaction force was increased with overhang length.

Dual chip memory package

Todays computer systems require more main memories than before due to the development of heavy-load softwares and the integration of multiple functions in a computer. However, since the computers became portable the sizes of computers are getting smaller. This means that it is necessary to put more memory chips into a limited space of the computers. In order to fulfil above requirement, a new high density package was developed, which looked the same as conventional plastic packages outside, and contained two chips inside, and named the Dual Chip Package (DCP). In packaging two chips in a package outline, chip-on-tape (COT) technology was combined with lead frames. The tape had wiring patterns inside and interconnection tabs along the periphery of the tape. The lead frames for the DCP were prepared by bonding the inner leads of the lead frames to the interconnection tabs of the tapes. Two chips are attached to the top side and the bottom side of the tape, and wire-bonded onto the tape surface. In the chip attachment and wire bonding process, one side of the tape was coated with an epoxy encapsulant to protect the chips during the wire bonding of the other side. After this process, the assembly processes were the same as those of conventional plastic packages. With DCP, it is possible to change the pin configurations of the package by varying the design of the tape. Reliability tests showed that the DCP met JEDEC level 3 requirement in pre-conditioning tests.

Designing a high speed system with amplitude and phase noise reduction effects

In this paper, we introduce a method for reducing the amplitude and the phase noise to achieve low noise and high speed system. Obtaining a good signal and maintaining the power integrity, by eliminating noise development and propagation are constant requirements. However, the increase of the interconnection complexity in the multilayer PCBs (Printed Circuit Boards) usually creates a questionable noise source that can be caused by either the signal mismatch or the power disturbance. Especially, the SSN (Simultaneous Switching Noise) and coupled noise need to be deliberately examined for reducing the overall noises. After the noise generation and propagation are analyzed, the amplitude and phase noise on the high speed signal will be investigated by using the integrated simulation circuit model (ISCM) technique and according to some related experiments. In this paper, we also propose a multi-PDN structure (M-PS) for minimizing the noise generation and propagation within the wanted frequency band. This method uses an additional core PDN to control the values of the R, L, and C parameters on the equivalent circuit of the systems PDN.

Board level reliability of novel Fan-in package on package(PoP)

The recent requirements for achieving higher memory density in a smaller package size have adopted 3D packaging of thin dies in a single package. However, increasing the number of dies in 3D stacking is limited by increasing the cost due to decrease die stacking yield. The known good package stacking can be solution to overcome such yield loss. In this study, a novel Fan-in PoP solution proposed, stacking two package which have stacked multiple dies each and interconnecting the package through blind EMC via without changing package size. The solder ball of top package fills up the blind EMC via during the reflow process. In order to evaluate the board level reliability, Fan-in PoP(QDP-DSP : Quad Die Package - Dual Stack Package) was mounted to a FR-4 board. Fan-in PoP with various solder compositions wes explored regarding the failure mode, crack propagation and life time under the drop test and thermal cycling test compared to those of ODP (Octa Die Package). The Fan-in PoP showed superior drop performance compared to ODP due to the package flexibility. On the other hand, thennal cycling test results showed a little increased life time compared to ODP. The solder joint formation on the silicon chip through blind EMC via causes the serious thermal stress concentration due to the silicon stiffness.