Young Hoon Son

Row-buffer decoupling: a case for low-latency DRAM microarchitecture

Modern DRAM devices for the main memory are structured to have multiple banks to satisfy ever-increasing throughput, energy-efficiency, and capacity demands. Due to tight cost constraints, only one row can be buffered (opened) per bank and actively service requests at a time, while the row must be deactivated (closed) before a new row is stored into the row buffers. Hasty deactivation unnecessarily re-opens rows for otherwise row-buffer hits while hindsight accompanies the deactivation process on the critical path of accessing data for row-buffer misses. The time to (de)activate a row is comparable to the time to read an open row while applications are often sensitive to DRAM latency. Hence, it is critical to make the right decision on when to close a row. However, the increasing number of banks per DRAM device over generations reduces the number of requests per bank. This forces a memory controller to frequently predict when to close a row due to a lack of information on future requests, while the dynamic nature of memory access patterns limits the prediction accuracy. In this paper, we propose a novel DRAM microarchitecture that can eliminate the need for any prediction. First, we identify that precharging the bitlines dominates the deactivate time, while sense amplifiers that work as a row buffer are physically coupled with the bitlines such that a single command precharges both bitlines and sense amplifiers simultaneously. By decoupling the bitlines from the row buffers using isolation transistors, the bitlines can be precharged right after a row becomes activated. Therefore, only the sense amplifiers need to be precharged for a miss in most cases, taking an order of magnitude shorter time than the conventional deactivation process. Second, we show that this row-buffer decoupling enables internal DRAM μ-operations to be separated and recombined, which can be exploited by memory controllers to make the main memory system more energy efficient. Our experiments demonstrate that row-buffer decoupling improves the geometric mean of the instructions per cycle and MIPS2/W by 14% and 29%, respectively, for memory-intensive SPEC CPU2006 applications.

Microbank: architecting through-silicon interposer-based main memory systems

Through-Silicon Interposer (TSI) has recently been proposed to provide high memory bandwidth and improve energy efficiency of the main memory system. However, the impact of TSI on main memory system architecture has not been well explored. While TSI improves the I/O energy efficiency, we show that it results in an unbalanced memory system design in terms of energy efficiency as the core DRAM dominates overall energy consumption. To balance and enhance the energy efficiency of a TSI-based memory system, we propose μbank, a novel DRAM device organization in which each bank is partitioned into multiple smaller banks (or μbanks) that operate independently like conventional banks with minimal area overhead. The μbank organization significantly increases the amount of bank-level parallelism to improve the performance and energy efficiency of the TSI-based memory system. The massive number of μbanks reduces bank conflicts, hence simplifying the memory system design. We evaluated a sophisticated prediction-based DRAM page-management policy, which can improve performance by up to 20.5% in a conventional memory system without μbanks. However, a μbank-based design does not require such a complex page-management policy and a simple open-page policy is often sufficient -- achieving within 5% of a perfect predictor. Our proposed μbank-based memory system improves the IPC and system energy-delay product by 1.62× and 4.80×, respectively, for memory-intensive SPEC 2006 benchmarks on average, over the baseline DDR3-based memory system.

CiDRA: A cache-inspired DRAM resilience architecture

Although aggressive technology scaling has allowed manufacturers to integrate Giga bits of cells into a cost-sensitive main memory DRAM device, these cells have become more defect-prone. With increased cell failure rates, conventional solutions such as populating spare DRAM rows and relying on error-correcting codes (ECCs) have shown limited success due to high area overhead, the latency penalties of data coding, and interference between ECC within a device (in-DRAM ECC) and other ECC across devices (rank-level ECC). In this paper, we propose CiDRA, a cache-inspired DRAM resilience architecture, which substantially reduces the area and latency overheads of correcting bit errors on random locations due to these faulty cells. We put a small SRAM cache within a DRAM device to replace accesses to the addresses including the faulty cells with ones that correspond to the cache data array. This CiDRA cache is paired with a Bloom filter to minimize the energy overhead of accessing the cache tags for every DRAM access and is also partitioned into small pieces, each being associated with the I/O pads for better area efficiency. Both the cache and DRAM banks are accessed in parallel while the banks are much slower. Consequently, the cache and filter are not in the critical path for normal DRAM accesses and incur no latency overhead. We also enhance the traditional in-DRAM ECC with error position bits and the appropriate error detecting capability while preventing interference with the traditional rank-level ECC scheme. By combining this enhanced in-DRAM ECC with the cache and Bloom filter, CiDRA becomes more area efficient because the in-DRAM ECC corrects most bit errors that are sporadic while the cache deals with the remaining relatively few pathological cases.

Chameleon: versatile and practical near-DRAM acceleration architecture for large memory systems

The performance of computer systems is often limited by the bandwidth of their memory channels, but further increasing the bandwidth is challenging under the stringent pin and power constraints of packages. To further increase performance under these constraints, various near-DRAM acceleration (NDA) architectures, which tightly integrate accelerators with DRAM devices using 3D/2.5D-stacking technology, have been proposed. However, they have not prevailed yet because they often rely on expensive HBM/HMC-like DRAM devices which also suffer from limited capacity, whereas the scalability of memory capacity is critical for some computing segments such as servers. In this paper, we first demonstrate that data buffers in a load-reduced DIMM (LRDIMM), which is originally developed to support large memory systems for servers, are supreme places to integrate near-DRAM accelerators. Second, we propose Chameleon, an NDA architecture that can be realized without relying on 3D/2.5D-stacking technology and seamlessly integrated with large memory systems for servers. Third, we explore three microarchitectures that abate constraints imposed by taking LRDIMM architecture for NDA. Our experiment demonstrates that a Chameleon-based system can offer 2.13 χ higher geo-mean performance while consuming 34% lower geo-mean data transfer energy than a system that integrates the same accelerator logic within the processor.

Dexamethasone downregulates caveolin-1 causing muscle atrophy via inhibited insulin signaling

Glucocorticoids play a major role in the development of muscle atrophy in various medical conditions, such as cancer, burn injury, and sepsis, by inhibiting insulin signaling. In this study, we report a new pathway in which glucocorticoids reduce the levels of upstream insulin signaling components by downregulating the transcription of the gene encoding caveolin-1 (CAV1), a scaffolding protein present in the caveolar membrane. Treatment with the glucocorticoid dexamethasone (DEX) decreased CAV1 protein and Cav1 mRNA expression, with a concomitant reduction in insulin receptor alpha (IRα) and IR substrate 1 (IRS1) levels in C2C12 myotubes. On the basis of the results of promoter analysis using deletion mutants and site-directed mutagenesis a negative glucocorticoid-response element in the regulatory region of the Cav1 gene was identified, confirming that Cav1 is a glucocorticoid-target gene. Cav1 knockdown using siRNA decreased the protein levels of IRα and IRS1, and overexpression of Cav1 prevented the DEX-induced decrease in IRα and IRS1 proteins, demonstrating a causal role of Cav1 in the inhibition of insulin signaling. Moreover, injection of adenovirus expressing Cav1 into the gastrocnemius muscle of mice prevented DEX-induced atrophy. These results indicate that CAV1 is a critical regulator of muscle homeostasis, linking glucocorticoid signaling to the insulin signaling pathway, thereby providing a novel target for the prevention of glucocorticoid-induced muscle atrophy.

Therapeutic Mechanisms of Human Adipose-Derived Mesenchymal Stem Cells in a Rat Tendon Injury Model

Background: Although survival of transplanted stem cells in vivo and differentiation of stem cells into tenocytes in vitro have been reported, there have been no in vivo studies demonstrating that mesenchymal stem cells (MSCs) could secrete their own proteins as differentiated tenogenic cells. Purpose/Hypothesis: Using a xenogeneic MSC transplantation model, we aimed to investigate whether MSCs could differentiate into the tenogenic lineage and secrete their own proteins. The hypothesis was that human MSCs would differentiate into the human tenogenic lineage and the cells would be able to secrete human-specific proteins in a rat tendon injury model. Study Design: Controlled laboratory study. Methods: The Achilles tendons of 57 Sprague Dawley rats received full-thickness rectangular defects. After the modeling, the defective tendons were randomly assigned to 3 groups: (1) cell group, implantation with human adipose-derived mesenchymal stem cells (hASCs) and fibrin glue (106 cells in 60 μL); (2) fibrin group, implantation with fibrin glue and same volume of cell media; and (3) sham group, identical surgical procedure without any treatment. Gross observation and biomechanical, histopathological, immunohistochemistry, and Western blot analyses were performed at 2 and 4 weeks after modeling. Results: hASCs implanted into the defective rat tendons were viable for 4 weeks as detected by immunofluorescence staining. Tendons treated with hASCs showed better gross morphological and biomechanical recovery than those in the fibrin and sham groups. Furthermore, the expression of both human-specific collagen type I and tenascin-C was significantly higher in the cell group than in the other 2 groups. Conclusion: Transplantation of hASCs enhanced rat tendon healing biomechanically. hASCs implanted into the rat tendon defect model survived for at least 4 weeks and secreted human-specific collagen type I and tenascin-C. These findings suggest that transplanted MSCs may be able to differentiate into the tenogenic lineage and contribute their own proteins to tendon healing. Clinical Relevance: In tendon injury, MSCs can enhance tendon healing by secreting their own protein and have potential as a therapeutic option in human tendinopathy.

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

Technology scaling has continuously improved the density, performance, energy efficiency, and cost of DRAM-based main memory systems. Starting from sub-20nm processes, however, the industry began to pay considerably higher costs to screen and manage notably increasing defective cells. The traditional technique, which replaces the rows/columns containing faulty cells with spare rows/columns, has been able to cost-effectively repair the defective cells so far, but it will become unaffordable soon because an excessive number of spare rows/columns are required to manage the increasing number of defective cells. This necessitates a synergistic application of an alternative resilience technique such as In-DRAM ECC with the traditional one. Through extensive measurement and simulation, we first identify that aggressive miniaturization makes DRAM cells more sensitive to random telegraph noise or variable retention time, which is dominantly manifested as a surge in randomly scattered single-cell faults. Second, we advocate using In-DRAM ECC to overcome the DRAM scaling challenges and architect In-DRAM ECC to accomplish high area efficiency and minimal performance degradation. Moreover, we show that advancement in process technology reduces decoding/correction time to a small fraction of DRAM access time, and that the throughput penalty of a write operation due to an additional read for a parity update is mostly overcome by the multi-bank structure and long burst writes that span an entire In-DRAM ECC codeword. Lastly, we demonstrate that system reliability with modern rank-level ECC schemes such as single device data correction is further improved by hundred million times with the proposed In-DRAM ECC architecture.

Scalable high-radix router microarchitecture using a network switch organization

As the system size of supercomputers and datacenters increases, cost-efficient networks become critical in achieving good scalability on those systems. High-radix routers reduce network cost by lowering the network diameter while providing a high bisection bandwidth and path diversity. The building blocks of these large-scale networks are the routers or the switches and they need to scale accordingly to the increasing port count and increasing pin bandwidth. However, as the port count increases, the high-radix router microarchitecture itself needs to scale efficiently. Hierarchical crossbar switch organization has been proposed where a single large crossbar used for a router switch is partitioned into many small crossbars and overcomes the limitations of conventional router microarchitecture. Although the organization provides high performance, it has limited scalability due to excessive power and area overheads by the wires and intermediate buffers. In this article, we propose scalable router microarchitectures that leverage a network within the switch design of the high-radix routers themselves. These alternative designs lower the wiring complexity and buffer requirements. For example, when a folded-Clos switch is used instead of the hierarchical crossbar switch for a radix-64 router, it provides up to 73%, 58%, and 87% reduction in area, energy-delay product, and energy-delay-area product, respectively. We also explore more efficient switch designs by exploiting the traffic-pattern characteristics of the global network and its impact on the local network design within the switch for both folded-Clos and flattened butterfly networks. In particular, we propose a bilateral butterfly switch organization that has fewer crossbars and global wires compared to the topology-agnostic folded-Clos switch while achieving better low-load latency and equivalent saturation throughput.

Real-Time Monitoring of Glutathione in Living Cells Reveals that High Glutathione Levels Are Required to Maintain Stem Cell Function

Summary The core functions of stem cells (SCs) are critically regulated by their cellular redox status. Glutathione is the most abundant non-protein thiol functioning as an antioxidant and a redox regulator. However, an investigation into the relationship between glutathione-mediated redox capacity and SC activities is hindered by lack of probe. Here, we demonstrate that cyanoacrylamide-based coumarin derivatives are ratiometric probes suitable for the real-time monitoring of glutathione levels in living SCs. These probes revealed that glutathione levels are heterogeneous among subcellular organelles and among individual cells and show dynamic changes and heterogeneity in repopulating SCs depending on oxidative stress or culture conditions. Importantly, a subpopulation of SCs with high glutathione levels exhibited increased stemness and migration activities in vitro and showed improved therapeutic efficiency in treating asthma. Our results indicate that high glutathione levels are required for maintaining SC functions, and monitoring glutathione dynamics and heterogeneity can advance our understanding of the cellular responses to oxidative stress.

4‐n‐butylresorcinol enhances proteolytic degradation of tyrosinase in B16F10 melanoma cells

4‐n‐butylresorcinol is a competitive inhibitor of tyrosinase and has been used as an antimelanogenic agent. However, its inhibition mechanism in intact cells is not fully understood. To elucidate the cellular mechanism, we compared in vitro and in vivo inhibitory effects of 4‐n‐butylresorcinol on tyrosinase activity.