Young-joon Choi

A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme

While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA.

A 117-mm/sup 2/ 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications

For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-/spl mu/m CMOS technology, resulting in a 117 mm/sup 2/ die size and a 1.1 /spl mu/m/sup 2/ effective cell size.

A High Performance Controller for NAND Flash-based Solid State Disk (NSSD)

NAND flash memory based solid-state disk (NSSD) has been used for industrial and military use due to its high reliability and shock resistance. With the bit cost reduction of flash memory and the explosive growth of flash market, NSSD is expected to penetrate into diverse applications such as mobile thin clients, car navigation systems and movie players, which prefer low power consumption, high reliability, high performance and so on. This paper mainly focuses on the development of a high performance and cost-efficient controller for NSSD, with the aim of describing both hardware and software architectures. In order to demonstrate the usefulness of the proposed approach, we show performance, power consumption and start-up time evaluation results over magnetic disks using third party benchmark tools

A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications

The NAND flash memory was originally designed to target solid-state mass storage applications. Key requirements of mass storage, low cost and high serial access throughput, have been achieved by sacrificing a non-critical feature, fast random access. For a quantum step in cost reduction, the multi-level cell is combined with NAND flash memory. This 128 Mb multi-level NAND flash memory stores two bits per cell by tight programmed cell threshold voltage (Vth) control and is made practical by significantly reducing program disturbs.The NAND flash memory was originally designed to target solid-state mass storage applications. Key requirements of mass storage, low cost and high serial access throughput, have been achieved by sacrificing a non-critical feature, fast random access. For a quantum step in cost reduction, the multi-level cell is combined with NAND flash memory. This 128 Mb multi-level NAND flash memory stores two bits per cell by tight programmed cell threshold voltage (Vth) control and is made practical by significantly reducing program disturbs.

A high speed programming scheme for multi-level NAND flash memory

A new scheme for page programming of multi-level NAND flash memory has been developed. It maintains the 528 byte page size of 32 Mb NAND flash memories with a high throughput of 0.5 MB/s. The circuitry has been successfully implemented into an experimental 128 Mb multi-level flash memory.

Future evolution of memory subsystem in mobile applications

As smart phones make for the focal point of todays ubiquitous computing, demands of increased memory performance for DRAM and Flash storage are surging while trying to suppress power consumption. New DRAM architectures such as Wide IO, serial I/O and combo are investigated in the industry. Fast read/write access to Flash storage is needed with the virtual memory system under multi-tasking. This paper discusses new DRAM architectures from the perspective of performance, power consumption, pin counts and others. The performance enhancement of Flash storage is discussed in optimizing the internal device for the system access pattern, and on the requirements of system software and storage interface scheme for dealing with multiple access queues.