Young-Si Hwang

A predictive dynamic power management technique for embedded mobile devices

It is becoming crucial to manage devices intelligently to reduce the power consumption of mobile embedded systems. Power-aware system management relies on techniques of collecting and analyzing information on the status of Input/Output (I/O) devices or processors while the system is running applications. However, the overhead of collecting information using software while the system is running is so huge that performance of the system may be severely degraded. Therefore, designing a Power Management Unit (PMU) that collects information and analyzes the information with some hardware support is very important. In this paper, we propose a novel PMU design that collects and analyzes access patterns to I/O devices while an application is being executed. We also propose a predictive power-aware management scheme which is carried out based on the collected information. Experiments with various applications have been conducted to show the effectiveness of our approach.

Dynamic Power Management Technique for Multicore Based Embedded Mobile Devices

As the proliferation of ubiquitous computing environments becomes a reality, the need for high speed data processing and intelligent system management increases rapidly. In particular, the need for low-power designs and power-aware system management is getting stronger. While multicore systems are deployed in many embedded system areas, an effective power management technique for multicores is not available yet. In this paper, we propose a novel power management technique based on a parallel programming model. OpenMP is a well-known programming paradigm for shared memory multicore systems. OpenMP is based on library routines for parallel processing. By identifying the invoked library routines, how many cores will be adequate for a certain application can be determined, and the number of necessary cores for a given task can be determined during run-time. By turning off unnecessary cores, we can reduce power consumption. We implemented this method by adding capabilities in an OpenMP-compliant compiler and conducted experiments with various benchmarks. We were able to reduce the power consumption by 18% on average compared to other conventional power management methods.

Virtual ARM Platform for embedded system developers

More and more embedded system developers and system-on-chip designers reply on microprocessor-based design methodology to reduce time-to market. ARM processor has been a major player in embedded system industry over the last 10 years. However, there are many restrictions on developing embedded software using ARM processor in the early design stage. For those who are not familiar with embedded software equipment, testing their software on a real ARM hardware platform is a challenging job. To overcome such a problem, we have designed virtual ARM platform, which offers easier testing and debugging environment to ARM based embedded system developers. Major benefits that can be achieved by utilizing a virtual ARM platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. Unlike many other purely software-oriented ARM simulators which are independent of real hardware platforms, our proposed virtual ARM platform is specifically targeted on SYS-Lab 5000 ARM hardware platform, (designed by Libertron, Inc.,) which means that virtual ARM platform imitates behaviors of embedded software as if the software is running on the target embedded hardware as closely as possible. This paper shows how virtual ARM platform is designed and how it can be used to reduce design time and cost.

Flexible framework for dynamic management of multi-core systems

In this paper, we propose a dynamic management framework for multi-core systems. Power management and temperature control are two crucial components for multi-core system control. Therefore, in this paper we propose a flexible and scalable framework which is very effective in reducing the power consumption and the temperature by adjusting the number of active cores on a Linux-based multi-core system. To manage the states of a multi-core system, both dynamic power management (DPM) and dynamic voltage/frequency scaling (DVFS) can be selectively applied depending on the type of cores. So unnecessary cores can be shut down or idling cores can be slowed down. To show the effectiveness and flexibility of our framework, we implemented the framework on both Intel Centrino Duo and ARM-11 MPCore platforms. By conducting various experiments with the proposed framework, we could successfully reduce the power consumption and the temperature.

Predictive power aware management for embedded mobile devices

Intelligent power management of mobile devices is getting more important as ubiquitous computing is coming true in daily life. Power aware system management relies on techniques of collecting and analyzing information on the status of I/O devices or processors while the system is running applications. However, the overhead of collecting information using software while the system is running is so huge that performance of the system may be severely deteriorated. Therefore, it is very crucial to design a PMU (power management unit) which collects information in hardware so that the performance of the system is not degraded. In this paper, we propose a novel PMU design which collects access patterns to I/O devices while an application is being executed. And a predictive power aware management is carried out based on the collected information. Experiments with various applications have been conducted to show the effectiveness of our approach.

Energy consumption prediction technique for embedded mobile device by using battery discharging pattern

As the end user requires more powerful functionality from the mobile device, the complexity of software running on the mobile device is increasing rapidly. Therefore, the performance of hardware components such as processor, memory and storage device which constitute mobile systems has been growing rapidly. On the other hand, battery capacity has shown little growth. Because battery lifetime is a major constraint for mobile systems, many researches have been done on reduce energy consumption. Reducing energy consumption should be based on precise energy consumption measurement. In this paper, we propose an accurate energy consumption estimation technique which is capable of modeling the energy consumption according to various combinations of device states without additional hardware.

A Test Method for Power Management of SoC-based Microprocessors

Power management in system-on-chip (SoC) has become one of the most crucial techniques for mobile devices. Among many intellectual properties (IPs) of SoC, a microprocessor, which is one of the major power consumers in the system, is a key component in SoC power management. Controlling idle states for microprocessors, which is typically implemented by combinations of clock gating and power gating, needs a testing method at operating system level after pre-silicon verification. When a microprocessor performs power state transitions, the microprocessors architectural state and the contents of local cache memory are corrupted. It cannot handle service requests from other peripheral IPs as well. Therefore, it is important to ensure that the system operates correctly with its original execution state after power state transitions. This paper addresses a testing methodology for power state switching of microprocessor at system level.

An efficient load balancing method for multi-core systems with asymmetric memory architectures

As the number of cores in a processor increases, asymmetrically distributed memory architecture is expected to become widely adopted. Running an application program in a distributed fashion on an asymmetric memory architecture effectively is a challenging task. In this paper, we propose a novel load balancing technique for multi-core systems with asymmetric memory architectures. The proposed method uses probabilistic information on the expected execution time of the child processes for each parent process. Also, to maximize the load balancing effect with low cost, the proposed method groups processes, and treats each group as a load balancing unit. The trade-off between load balancing effect of each load balancing unit and the cost is taken into account. To show the effectiveness of this paper, we present test cases in which the proposed method show better performance than that of existing load balancing methods.

Novel dynamic power management technique for multi-core based mobile devices

In this paper, we address a novel system-level low power management technique which is specifically targeted for an ARM 11 MPCore system. Our proposed solution is a DPM technique which includes process monitoring, real time power analysis, and policy application to reduce the power consumption while meeting the performance requirement. One of the main contributions of this paper is that we systematically infer QoS requirements of processes without getting any additional information from the application. When multiple processes are running under various user-level policies, priorities of the policy application are determined in such a way that the overall system performance is maintained while power consumption is effectively managed. Experimental results show that our DPM technique is very effective in reducing power consumption without violating systems QoS requirements.