Youngho Ahn

Flexible framework for dynamic management of multi-core systems

In this paper, we propose a dynamic management framework for multi-core systems. Power management and temperature control are two crucial components for multi-core system control. Therefore, in this paper we propose a flexible and scalable framework which is very effective in reducing the power consumption and the temperature by adjusting the number of active cores on a Linux-based multi-core system. To manage the states of a multi-core system, both dynamic power management (DPM) and dynamic voltage/frequency scaling (DVFS) can be selectively applied depending on the type of cores. So unnecessary cores can be shut down or idling cores can be slowed down. To show the effectiveness and flexibility of our framework, we implemented the framework on both Intel Centrino Duo and ARM-11 MPCore platforms. By conducting various experiments with the proposed framework, we could successfully reduce the power consumption and the temperature.

Design of OpenCL framework for embedded multi-core processors

In modern mobile embedded systems, various energy-efficient hardware acceleration units are employed in addition to a multi-core CPU. To fully utilize the computational power in such heterogeneous systems, Open Computing Language (OpenCL) has been proposed. A key benefit of OpenCL is that it works on various computing platforms. However, most vendors offer OpenCL software development kits (SDKs) that support their own computing platforms. The study of the OpenCL framework for embedded multi-core CPUs is in a rudimentary stage. In this paper, an OpenCL framework for embedded multi-core CPUs that dynamically redistributes the time-varying workload to CPU cores in real time is proposed. A compilation environment for both host programs and OpenCL kernel programs was developed and OpenCL libraries were implemented. A performance evaluation was carried out with respect to various definitions of the device architecture and the execution model. When running on embedded multi-core CPUs, applications parallelized by OpenCL C showed much better performance than the applications written in C without parallelization. Furthermore, since programmers are capable of managing hardware resources and threads using OpenCL application programming interfaces (APIs) automatically, highly efficient computing both in terms of the performance and energy consumption on a heterogeneous computing platform can be easily achieved.

Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation

In this paper, we propose a low-power adaptive low-density parity check (LDPC) decoder that utilizes dynamic voltage and frequency scaling to reduce power consumption. Most existing adaptive LDPC decoders have focused only on the decoding performance based on the signal-to-noise ratio (SNR) estimation. However, significant idle power is consumed when the decoder awaits the next frame after processing a frame. In mobile communication standards such as China Mobile Multimedia Broadcasting and Digital Video Broadcasting Satellite Second Generation, adaptive coding and modulation has been adopted. Thus, it is possible to reduce the power consumption efficiently by using the SNR estimation. In this paper, we apply a customized frequency selection scheme and a variable voltage generation scheme to an adaptive LDPC decoder to reduce the dynamic power consumption. The proposed schemes result in a reduction of 44% in the energy consumption of an LDPC decoder implemented using 0.18-μm complementary metal-oxide-semiconductor technology.

A novel load balancing method for multi-core with non-uniform memory architecture

As the number of cores in a processor increases, asymmetrically distributed memory architecture is expected to become widely adopted. Running an application program effectively in a distributed fashion on asymmetric memory architecture is a challenging task. In this paper, we propose a novel load balancing technique for multi-core systems with asymmetric memory architectures. The proposed method uses probabilistic information on the expected execution time of the child processes for each parent process. Also, to maximize the load balancing effect with low cost, the proposed method groups processes, and treats each group as a load balancing unit. The trade-off between load balancing effect of each load balancing unit and the cost is taken into account. To show the effectiveness of this paper, we present test cases in which the proposed method show better performance than that of existing load balancing methods.

User-Centric Power Management for Embedded CPUs Using CPU Bandwidth Control

Dynamic power management for mobile processors has become very important due to the increased clock speed and number of cores. There have been various power management governors using dynamic voltage and frequency scaling (DVFS). Among them, a user-centric power management has received a lot of attention as a method to save power while maintaining the quality of user experience (UX) referring to the perceived quality of system services to end users. Most user-centric governors have employed DVFS as a method to reduce the power consumption. However, DVFS may not be adequate enough to guarantee UX qualities for all task because the CPU clock speed changed by DVFS can affect all tasks running at the same processor. In order to minimize such inter-task interferences by DVFS, it is necessary to employ task-specific power management methods. This paper shows that CPU bandwidth control developed for CPU resource management within Linux kernel can be employed as a task-specific power management method, and a novel CPU power management scheme employing both DVFS and CPU bandwidth control is proposed. Experimental results show that the proposed governor can reduce the power consumption more than the Ondemand governor can achieve while maintaining the quality of UX.

Energy consumption prediction technique for embedded mobile device by using battery discharging pattern

As the end user requires more powerful functionality from the mobile device, the complexity of software running on the mobile device is increasing rapidly. Therefore, the performance of hardware components such as processor, memory and storage device which constitute mobile systems has been growing rapidly. On the other hand, battery capacity has shown little growth. Because battery lifetime is a major constraint for mobile systems, many researches have been done on reduce energy consumption. Reducing energy consumption should be based on precise energy consumption measurement. In this paper, we propose an accurate energy consumption estimation technique which is capable of modeling the energy consumption according to various combinations of device states without additional hardware.

A Test Method for Power Management of SoC-based Microprocessors

Power management in system-on-chip (SoC) has become one of the most crucial techniques for mobile devices. Among many intellectual properties (IPs) of SoC, a microprocessor, which is one of the major power consumers in the system, is a key component in SoC power management. Controlling idle states for microprocessors, which is typically implemented by combinations of clock gating and power gating, needs a testing method at operating system level after pre-silicon verification. When a microprocessor performs power state transitions, the microprocessors architectural state and the contents of local cache memory are corrupted. It cannot handle service requests from other peripheral IPs as well. Therefore, it is important to ensure that the system operates correctly with its original execution state after power state transitions. This paper addresses a testing methodology for power state switching of microprocessor at system level.

A Technique for Fast Process Creation Based on Creation Location

Due to the proliferation of software parallelization on multi-core CPUs, the number of concurrently executing processes is rapidly increasing. Unlike processes running in a server environment, those executing in a multi-core desktop or a multi-core mobile platform have various correlations. Therefore, it is crucial to consider correlations among concurrently running processes. In this paper, we exploit the property that for a given created location in the binary image of the parent process, the average running time of child processes residing in the run-queue differs. We claim that this property can be exploited to improve the overall system performance by running processes that have a relatively short running time before those with a longer running time. Experimental results verified that the running time was actually improved by 11%.

An efficient load balancing method for multi-core systems with asymmetric memory architectures

As the number of cores in a processor increases, asymmetrically distributed memory architecture is expected to become widely adopted. Running an application program in a distributed fashion on an asymmetric memory architecture effectively is a challenging task. In this paper, we propose a novel load balancing technique for multi-core systems with asymmetric memory architectures. The proposed method uses probabilistic information on the expected execution time of the child processes for each parent process. Also, to maximize the load balancing effect with low cost, the proposed method groups processes, and treats each group as a load balancing unit. The trade-off between load balancing effect of each load balancing unit and the cost is taken into account. To show the effectiveness of this paper, we present test cases in which the proposed method show better performance than that of existing load balancing methods.

Novel dynamic power management technique for multi-core based mobile devices

In this paper, we address a novel system-level low power management technique which is specifically targeted for an ARM 11 MPCore system. Our proposed solution is a DPM technique which includes process monitoring, real time power analysis, and policy application to reduce the power consumption while meeting the performance requirement. One of the main contributions of this paper is that we systematically infer QoS requirements of processes without getting any additional information from the application. When multiple processes are running under various user-level policies, priorities of the policy application are determined in such a way that the overall system performance is maintained while power consumption is effectively managed. Experimental results show that our DPM technique is very effective in reducing power consumption without violating systems QoS requirements.