Youngin Jeon

Top-Down Fabrication of Fully CMOS-Compatible Silicon Nanowire Arrays and Their Integration into CMOS Inverters on Plastic

A route to the top-down fabrication of highly ordered and aligned silicon nanowire (SiNW) arrays with degenerately doped source/drain regions from a bulk Si wafer is presented. In this approach, freestanding n- and p-SiNWs with an inverted triangular cross section are obtained using conventional photolithography, crystal orientation dependent wet etching, size reduction oxidation, and ion implantation doping. Based on these n- and p-SiNWs transferred onto a plastic substrate, simple SiNW-based complementary metal-oxide-semiconductor (CMOS) inverters are constructed for the possible applications of these SiNW arrays in integrated circuits on plastic. The static voltage transfer characteristic of the SiNW-based CMOS inverter exhibits a voltage gain of ∼9 V/V and a transition of 0.32 V at an operating voltage of 1.5 V with a full output voltage swing between 0 V and V(DD), and its mechnical bendability indicates good fatigue properties for potential applications of flexible electronics. This novel top-down approach is fully compatible with the current state-of-the-art Si-based CMOS technologies and, therefore, offers greater flexibility in device design for both high-performance and low-power functionality.

Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications

Based on experimental and simulation studies to gain insight into the suppression of ambipolar conduction in two distinct tunnel field-effect transistor (TFET) devices (that is, an asymmetric source-drain doping or a properly designed gate underlap), here we report on the fabrication and electrical/mechanical characterization of a flexible complementary TFET (c-TFET) inverter on a plastic substrate using multiple silicon nanowires (SiNWs) as the channel material. The static voltage transfer characteristic of the SiNW c-TFET inverter exhibits a full output voltage swing between 0 V and Vdd with a high voltage gain of ∼29 and a sharp transition of 0.28 V at Vdd = 3 V. A leakage power consumption of the SiNW c-TFET inverter in the standby state is as low as 17.1 pW for Vdd = 3 V. Moreover, its mechanical bendability indicates that it has good fatigue properties, providing an important step towards the realization of ultralow-power flexible logic circuits.

Flexible Nano-Floating-Gate Memory With Channels of Enhancement-Mode Si Nanowires

The electrical characteristics of a flexible nano-floating-gate memory (NFGM) device with a channel made of an enhancement-mode n+-p-n+ Si nanowire (Si-NW) are investigated in this work. The NFGM based on the enhancement-mode Si-NW field-effect transistor is constructed on a plastic substrate with a Pt-nanocrystal floating-gate layer; it exhibits an on-current/off-current ratio of ~107 and a subthreshold swing of 88 mV/dec. The NFGM shows good memory characteristics and mechanical flexibility, such as a threshold voltage shift of 1.85 V, a retention time of up to ~104s, and a stability for up to 1000 bending cycles. The present study demonstrates the promising potential of flexible Si-NW-based nonvolatile memories for future electronics.

Strain-Dependent Characteristics of Triangular Silicon Nanowire-Based Field-Effect Transistors on Flexible Plastics

Top-gate field-effect transistors (FETs) based on triangular silicon nanowires (SiNWs) obtained from a silicon bulk wafer using a conventional silicon manufacturing technology are constructed on flexible plastic substrates. Their field-effect mobility and peak transconductance are enhanced by 10% in the upwardly bent state and by 29% in the downwardly bent state at a strain of 1.02%, compared with the flat state. The strain effect resulting from the bending of the flexible substrates is higher in the downward state than in the upward state, and the increase in strain improves the performance of SiNW-based FETs. Moreover, their device performance is stable even after bending the substrate several thousand times.

Si-based flexible memristive systems constructed using top-down methods.

Si-based memristive systems consisting of Ag, amorphous Si, and heavily doped p-type Si nanowires were successfully constructed on plastic substrates through top-down methods, including the crystallographic wet etching of Si wafers, transfer onto plastic substrates, and thin film patterning. The memristive systems showed excellent memory characteristics and flexibility, such as intrinsic hysteric and rectifying behaviors, on/off resistance ratios of >1 × 10(5), and durability for up to 1000 bending cycles. The correlations between the Ag-filament-related nanostructures formed in amorphous Si and the resistance-switching behaviors were carefully examined with the tunneling current model, transmission electron microscopy, and secondary ion mass spectroscopy to explore the switching mechanism. Our study suggests the promising potential of the Si-based memristive systems for the development of next-generation flexible nonvolatile memory.

Switching Characteristics of Nanowire Feedback Field-Effect Transistors with Nanocrystal Charge Spacers on Plastic Substrates

In this study, we demonstrate the abruptly steep-switching characteristics of a feedback field-effect transistor (FBFET) with a channel consisting of a p(+)-i-n(+) Si nanowire (NW) and charge spacers of discrete nanocrystals on a plastic substrate. The NW FBFET shows superior switching characteristics such as an on/off current ratio of ∼10(5) and an average subthreshold swing (SS) of 30.2 mV/dec at room temperature. Moreover, the average SS and threshold voltage values can be adjusted by programming. These sharp switching characteristics originate from a positive feedback loop generated by potential barriers in the intrinsic channel area. This paper describes in detail the switching mechanism of our device.

Flexible Logic Gates Composed of Si-Nanowire-Based Memristive Switches

The flexible logic circuit configured using Si-based memristive switches is demonstrated. The memristive switches consisting of Ag/a-Si/heavily doped p-type Si are constructed on plastic using top-down-fabricated Si nanowires. The logic gate analyses provide insight toward logic circuits having multifunctionality and high connectivity through a crossbar-array architecture. With the strong stability of the logic performances against external strain, the memristive switch looks promising as a building block for flexible electronics.

Steep Subthreshold Swing n- and p-Channel Operation of Bendable Feedback Field-Effect Transistors with p+–i–n+ Nanowires by Dual-Top-Gate Voltage Modulation

In this study, we present the steep switching characteristics of bendable feedback field-effect transistors (FBFETs) consisting of p(+)-i-n(+) Si nanowires (NWs) and dual-top-gate structures. As a result of a positive feedback loop in the intrinsic channel region, our FBFET features the outstanding switching characteristics of an on/off current ratio of approximately 10(6), and point subthreshold swings (SSs) of 18-19 mV/dec in the n-channel operation mode and of 10-23 mV/dec in the p-channel operation mode. Not only can these devices operate in n- or p-channel modes, their switching characteristics can also be modulated by adjusting the gate biases. Moreover, the device maintains its steep SS characteristics, even when the substrate is bent. This study demonstrates the promising potential of bendable NW FBFETs for use as low-power components in integrated circuits or memory devices.

Flexible semi-around gate silicon nanowire tunnel transistors with a sub-kT/q switch

Tunnel field-effect transistors (TFETs) with a subthreshold swing (SS) < 60 mV/dec are expected to be active devices in low-power flexible systems, potentially lowering operational voltage by virtue of steep switching behavior via band-to-band tunneling. In silicon (Si) channel materials, however, it still remains a challenge to obtain SS smaller than 60 mV/dec. In this study, we experimentally demonstrate the sub-60 mV/dec operation of a flexible semi-around gate TFET on a plastic substrate using Si nanowires (SiNWs) as the channel material. With the combined advantages of selectively thinned SiNW channels (width ∼ 15 nm and height ∼ 40 nm) and high-κ (Al2O3 ∼ 7 nm) gate dielectric, in conjunction with an abrupt degenerate source junction, the device with a channel length of ∼500 nm exhibits a minimal SS of ∼42 mV/dec at room temperature. Moreover, mechanical bendability of the device indicates that it has stable and good fatigue properties, providing an important step towards the realization of steep-slope switches for low-power and energy-efficient flexible electronics.

Impact-Ionization and Tunneling FET Characteristics of Dual-Functional Devices With Partially Covered Intrinsic Regions

Dual-functional devices based on gated p-i-n diodes are proposed in this simulation study. The dual-functional devices function not only as n-channel tunneling field-effect transistors (nTFETs) but also as p-channel impact-ionization FETs (p-IFETs), depending on the bias conditions. In this study, the I-V characteristics, subthreshold swing (SS), ON/OFF current ratio (Ion/Ioff), and band diagram are analyzed using a device simulator (Silvaco Atlas), and the features of the n-TFETs and the p-IFETs are extracted from the simulated data. The n-TFETs exhibit high Ion/Ioff of ~1011 and a sub-60-mV/dec SS, and the p-IFETs yield extremely low SS of as small as 8.57 mV/dec. Our approach is one of the useful methods to design multifunctional electronics for lowering the power consumption.