Yu Daquan

Simulation of through via bottom—up copper plating with accelerator for the filling of TSVs

Filling high aspect ratio through silicon vias (TSVs) without voids and seams by copper plating is one of the technical challenges for 3D integration. Bottom—up copper plating is an effective solution for TSV filling. In this paper, a new numerical model was developed to simulate the electrochemical deposition (ECD) process, and the influence of an accelerator in the electrolyte was investigated. The arbitrary Lagrange—Eulerian (ALE) method for solving moving boundaries in the finite element method (FEM) was used to simulate the electrochemical process. In the model, diffusion coefficient and adsorption coefficient were considered, and then the time-resolved evolution of electroplating profiles was simulated with ion concentration distribution and the electric current density.

High-speed through-silicon via filling method using Cu-cored solder balls

A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture. Cu-cored solder balls with a total diameter of 100 μm were used to fill 150 μm deep, 110 μm wide vias in silicon. The wafer-level filling process can be completed in a few seconds, which is much faster than using the traditional electroplating process. Thermo-mechanical analysis of via filling using solder, Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials. It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.