Wan Lixi

High-speed through-silicon via filling method using Cu-cored solder balls

A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture. Cu-cored solder balls with a total diameter of 100 μm were used to fill 150 μm deep, 110 μm wide vias in silicon. The wafer-level filling process can be completed in a few seconds, which is much faster than using the traditional electroplating process. Thermo-mechanical analysis of via filling using solder, Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials. It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.

An equivalent model of TSV silicon interposer

The silicon layer containing through silicon vias (TSVs) is considered as anisotropic fiber reinforced composite layer with different longitudinal and transversal properties. An analytical approach is presented to estimate the effective Youngs modulus, Poissons ratio and coefficient of thermal expansion (CTE) for composite layer. It shows that the TSVs have no significant influence on the deflection of silicon layer, and the model ignoring TSVs is capable to predict enough accurate deflection of silicon layer.

The impact of wire bonding on the transmission performance of high-speed links in SiP

Wire bonding is a primary method of making interconnection between an integrated circuit (IC) and a printed circuit board (PCB) during semiconductor device fabrication, which is generally considered as the most flexible and cost-effective interconnection technology, and is widely used in electric packaging. This paper focuses on the impedance mismatch problem caused by bonding wires. A variety of bonding wires with different characteristics in terms of diameter, loop span, loop height, and shape are studied in this paper. Additionally, the crosstalk between adjacent bonding wires is analyzed. All analysis is founded on the base of signal integrity theory and simulation with HFSS software.

Interfacial stress in Through Silicon Vias

Through Silicon Via (TSV) has emerged as a good solution to provide high density interconnections in three-dimensional packaging interconnect technologies. However, the thermal-mechanical reliability is a big issue. When the TSV is subjected to thermal load, large stress and strain would be created at the interface of the materials because of the great mismatch of CTE. In this paper, an axi-symmetric single TSV model with RDL layer is taken into consideration. A static temperature difference of Δt=165°C is carried out to simulate the thermal stress, effects of via size and the interposer height on the stress are investigated. Effect of SiO2 layer on Cu and Si is also analyzed. In addition, the shear stress of interface, under thermal cycles from -40°C to 125°C, is computed. In the simulation model, the kinematic hardening material model of Cu is used.

A novel wirebond-BGA CPU package

The evolution of microprocessor packaging continues to be driven by ever increasing performance, economics and different market segment requirements. CPU evolution in performance/cost is driving the packaging technology continuously. Institute of Microelectronics, Chinese Academy of Sciences has implemented the CPU packaging in 2010. The fabricated package meets all the requirements by Loongson Company, and becomes the first fully domestically packaged CPU in China.

Effects of via pitch on silicon stress in TSV interposer

Through silicon vias (TSVs) have been extensively studied because it is a key enabling technology for achieving three dimensional (3D) chip stacking and silicon interposer interconnection. The large mismatch between the coefficients of thermal expansion (CTE) of copper and silicon induces stress which is critical for the TSV reliability performance. This paper proposes analytical solutions of stress in a single TSV subjected to thermal loading. Then the thermal stress interaction between the vias induced on silicon has been investigated using finite element modeling. It indicates that the interaction of thermal stress between vias becomes insignificant as long as the ratio of pitch to diameter of TSVs reaches three.

Fabrication of PN junction capacitor using SiP technology on Si-based interposer wafer

The article relates to the fabrication of embedded P-N junction capacitors, using System-in-Package (SiP) technology, on a silicon interposer wafer with Through-Silicon-Via (TSV). The P-N junction capacitors are fabricated using current micromachining technologies, including etching high aspect-ratio, three-dimensional honeycomb structure and thermal oxidation, thermal dopant diffusion, sputtering, and metallization and so on. The fabricated capacitor displays high capacitance density compared with common two-dimensional (2D) P-N junction capacitors. Tests at high frequency (10 Mhz–40 GHz) were conducted to evaluate the properties of these capacitors. Test results show that the capacitors have a high capacitance density up to 12nF/mm2 of wafer area, with reverse bias voltage of 1V, which is about 10–12 times that of 2D semiconductor capacitors, and is attributed to the increased junction area inherent in the three-dimensional via structure. These capacitors can be used for decoupling under a wide frequency range from 300 MHz to 3.2 GHz. they show a low parasitic inductance by measuring. Capacitor has a characteristic that capacitance value also keeps up constant with the increase of frequency.

Characteristics of high frequency and high density through silicon vias (TSVs)

TSV has now been a hotspot of the industry for years. Comparing with the wire-bonding, the technology populated in the last decade, Through Silicon Via (TSV) has merits of shorter wiring route, better signal integrity, larger bandwidth, lower power consumption and smaller packaging size. Undoubtedly, the TSV is treated by the industry to be the next generation of packaging solution to replace the wire-bonding. However, the TSV engineering has to conquer several difficulties, e.g. drilling technique, via filling technique, via filling material, stacking and bonding technique, and handling after the wafer thinning, etc. Therefore the standardization of the TSV still has a long way to go. This paper illustrates the initial achievement concerning with via filling material and corresponding high frequency and high density advantages that acquired by Institute of Microelectronics, Chinese Academy of Sciences.