Dai Fengwei

High-speed through-silicon via filling method using Cu-cored solder balls

A novel low-cost and high-speed via filling method using Cu-cored solder balls was investigated for through-silicon via manufacture. Cu-cored solder balls with a total diameter of 100 μm were used to fill 150 μm deep, 110 μm wide vias in silicon. The wafer-level filling process can be completed in a few seconds, which is much faster than using the traditional electroplating process. Thermo-mechanical analysis of via filling using solder, Cu and Cu-cored solder was carried out to assess the thermo-mechanical properties of the different filling materials. It was found that the vias filled with Cu-cored solder exhibit less thermal-mechanical stresses than solder-filled vias, but more than Cu-filled vias.

Investigation of silicon stress around through silicon vias by high efficiency micro-Raman microscopy

Through silicon vias (TSVs) attract considerable amount of attention and activity in recent years as a main means to achieve three-dimensional (3D) integrated circuit (IC) functionality. However, the new technology poses new integration challenges as well as new reliability challenges. This paper presents the latest progress in TSV non-destructive stress testing by means of micro-Raman microscopy, a technique which is approved to be the method of choice for identifying stress on silicon surface. The principle of micro-Raman microscopy for TSV measurement is illustrated. By using commercially available micro-Raman microscopy tools, silicon stress around vias having a diameter of 30 μm and a depth of 160 μm has been visualized under optimized conditions.

Fabrication of PN junction capacitor using SiP technology on Si-based interposer wafer

The article relates to the fabrication of embedded P-N junction capacitors, using System-in-Package (SiP) technology, on a silicon interposer wafer with Through-Silicon-Via (TSV). The P-N junction capacitors are fabricated using current micromachining technologies, including etching high aspect-ratio, three-dimensional honeycomb structure and thermal oxidation, thermal dopant diffusion, sputtering, and metallization and so on. The fabricated capacitor displays high capacitance density compared with common two-dimensional (2D) P-N junction capacitors. Tests at high frequency (10 Mhz–40 GHz) were conducted to evaluate the properties of these capacitors. Test results show that the capacitors have a high capacitance density up to 12nF/mm2 of wafer area, with reverse bias voltage of 1V, which is about 10–12 times that of 2D semiconductor capacitors, and is attributed to the increased junction area inherent in the three-dimensional via structure. These capacitors can be used for decoupling under a wide frequency range from 300 MHz to 3.2 GHz. they show a low parasitic inductance by measuring. Capacitor has a characteristic that capacitance value also keeps up constant with the increase of frequency.

Characteristics of high frequency and high density through silicon vias (TSVs)

TSV has now been a hotspot of the industry for years. Comparing with the wire-bonding, the technology populated in the last decade, Through Silicon Via (TSV) has merits of shorter wiring route, better signal integrity, larger bandwidth, lower power consumption and smaller packaging size. Undoubtedly, the TSV is treated by the industry to be the next generation of packaging solution to replace the wire-bonding. However, the TSV engineering has to conquer several difficulties, e.g. drilling technique, via filling technique, via filling material, stacking and bonding technique, and handling after the wafer thinning, etc. Therefore the standardization of the TSV still has a long way to go. This paper illustrates the initial achievement concerning with via filling material and corresponding high frequency and high density advantages that acquired by Institute of Microelectronics, Chinese Academy of Sciences.