Yu Fujita

Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology

For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator called Cool Mega Array (CMA)-SOTB is implemented by using Silicon on Thin BOX (SOTB), a new process technology developed by the Low-power Electronics Association & Project (LEAP). A real chip using a 65nm experimental process achieved a sustained performance of 192MOPS with a power supply of 0.4V and power consumption of 1.7mW. A clock frequency of 89MHz was achieved with a power supply of just 0.4V when a forward bias voltage was given. When using a reverse bias, the leakage current could be suppressed to less than 20μW in the stand-by mode. The key concept of CMA-SOTB is maintaining a balance between performance and leakage current by independently controlling the bias voltages of the PE array and the microcontroller. Evaluations of the operational frequency and power consumption of filter application programs shed light on how to find the combination of bias voltages that achieves the best energy efficiency for a required performance. The range of advantageous power supply voltage for a required performance considering the body bias was also found.

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Body bias control is an efficient means of balancing the trade-off between leakage power and performance especially for chips with silicon on thin buried oxide (SOTB), a type of FD-SOI technology. In this work, a method for finding the optimal combination of the supply voltage and body bias voltage to the core and memory is proposed and applied to a real micro-controller chip using SOTB CMOS technology. By obtaining several coefficients of equations for leakage power, switching power and operational frequency from the real chip measurements, the optimized voltage setting can be obtained for the target operational frequency. The power consumption lost by the error of optimization is 12.6% at maximum, and it can save at most 73.1% of power from the cases where only the body bias voltage is optimized. This method can be applied to the latest FD-SOI technologies.

Body bias grain size exploration for a coarse grained reconfigurable accelerator

This paper explores the grain of domain size of an energy efficient coarse grained reconfigurable array called CMA (Cool Mega Array). By using Genetic Algorithm based body bias assignment method, the leakage reduction of various grain size was evaluated. As a result, a domain with 2×1 PEs achieved about 40% power reduction with a 6% area overhead.

Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB

For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator called Cool Mega Array (CMA)-SOTB is implemented by using Silicon on Thin BOX (SOTB), a new process technology developed by the Low-power Electronics Association & Project (LEAP). This chip has three voltages for controlling power and performance, supply voltage, PE-Array body bias voltage and microcontroller body bias voltage. In order to find the optimal operational point for a given requirement, a large effort for measurements and adjustments is required. This paper proposes power model for finding the optimal operation point from several measurement results. From the proposed model, the power can be estimated with 4.4% difference from the measured value on average. By using the model, the optimal source voltage and body bias voltages for PE-array and microcontroller can be obtained for a given operational frequency. Compared with the result of the exhaustive search, 37.4% of energy is saved with much small effort of measurements.

A Thermal Management System for Building Block Computing Systems

Cube-1 is a heterogeneous multiprocessor consisting of 3D stacked chips connecting with inductive coupling through chip interface (TCI). The most important problem of Cube-1 is the thermal management. Unlike TSV which can be used for heat dissipation, stacked chips are electrically contactless in inductive coupling TCI. First, by measuring the relationship between the chip temperature and leakage monitor, we examined that the leakage monitor can be used as a temperature sensor of the chip. Then, we measured the thermal characteristics of Cube-1 by leakage moniters. The chip temperature change due to the internal power was evaluated, and it appeared that the chip temperature was not changed with this level of power consumption even if the chip was sandwiched with other chips. The heat conductance through the stacked chip was also evaluated. Evaluation results show that the heat dissipation of the chip sandwiched with other chips is almost the same as that of the chip placed top on the stack. Finally, we proposed the supply voltage control system of the stacked chip by making the best use of the chip temperature data from the leakage monitor. By using the proposed control, the energy efficiency can be improved by 5% at maximum.

Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET

In this brief, a practical power optimization method that calculates the optimal power supply and body bias voltages, for a given target operational frequency and a temperature, is proposed and evaluated. The proposed optimization method is based upon a simple power model in which several coefficients for leakage power, switching power, temperature, and operational frequency are obtained from accurate real chip measurements. The calculated optimal-voltage settings by the proposed model can achieve minimum accuracies of 93.8%, 91.6%, and 79.5% for room-temperature, 50 °C, and 65 °C, respectively. Since the proposed methodology is based on well-known power formulas, it can be applied to the latest FD-SOI technologies.

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Cool Mega Array (CMA)-SOTB-2 is an ultra-low energy Coarse Grained Reconfigurable Architecture[1] (CGRA) for recent advanced sensor networks, Internet of Things and wearable computing. It has a large Processing Element (PE) array without memory elements for mapping an applications data-flow graph, a small simple programmable μ-controller for data management, and data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. It is implemented by using Silicon on Thin BOX (SOTB) CMOS, a new process technology developed by the Low-power Electronics Association & Project (LEAP).

3D Shared Bus Architecture Using Inductive Coupling Interconnect

Attention has been focused on 3D chip stacking for reducing the semiconductor area per chip while maintaining the overall performance. By using inductive coupling wireless Thru-Chip Interface (TCI) in chip stack for a 3D multiprocessor, the replacement/addition/removing of chips is made possible using the inductive coupling wireless TCI in the chip stack for a 3D multiprocessor and thus, high flexibility is provided. A bus can be easily formed with the TCI by stacking duplex wired coils in the same place on the stacked chip. However, traditional static time division multiple access (STDMA) cannot make use of the potential bus bandwidth, while dynamic time division multiple access (DTDMA) requires a lot of coils that cannot be efficiently used for the control signals. We propose an asynchronous TDMA bus (A-TDMA bus) that uses the CSMA/CD protocol and a resonant synchronous TDMA bus (RS-TDMA bus) that uses a resonant synchronized clock and a look-ahead technique to improve the use of the bandwidth of a 3D shared bus. The results of a network simulation using the GEM5 simulator showed that the zero-load latency of both proposed methods was reduced by 29% in a four-chip stack and 50% in an eight-chip stack compared to that of STDMA. A full system simulation using GEM5 shows that the execution time of the proposed methods decreased by 6.5% in the four-chip stack and 17% in the eight-chip stack compared with that of STDMA.

Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery

Cool mega array with silicon on thin box (CMA-SOTB) is an extremely low power coarse grained reconfigurable accelerator. It was implemented by using the SOTB technology developed by a Japanese national project, low-power electronics association & project (LEAP). Making the best use of such a device and low energy architectural techniques, CMA-SOTB works more than 25MHz clock with less than 0.3V supply voltage. Various kind of optimization can be done by controlling the body bias voltage for PE array and micro-controller independently. The demonstration using CMA-SOTB first shows that a simple image processing application can work with a 0.25V-0.4V solar battery. Then the leakage power control by changing the body bias is demonstrated. In the stand-by mode, less than 20μW power is consumed by using strong reverse bias.