Hayate Okuhara

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Body bias control is an efficient means of balancing the trade-off between leakage power and performance especially for chips with silicon on thin buried oxide (SOTB), a type of FD-SOI technology. In this work, a method for finding the optimal combination of the supply voltage and body bias voltage to the core and memory is proposed and applied to a real micro-controller chip using SOTB CMOS technology. By obtaining several coefficients of equations for leakage power, switching power and operational frequency from the real chip measurements, the optimized voltage setting can be obtained for the target operational frequency. The power consumption lost by the error of optimization is 12.6% at maximum, and it can save at most 73.1% of power from the cases where only the body bias voltage is optimized. This method can be applied to the latest FD-SOI technologies.

Variable pipeline structure for Coarse Grained Reconfigurable Array CMA

Cool mega-array (CMA) is a kind of coarse grained reconfigurable architecture (CGRA) which has shown its ability of ultra low-power computation. However, as CMA completely eliminates clock trees and registers, the performance improvement has been limited. In this paper, we introduce a variable pipeline structure to CMA with the minimum essential registers to provide more wide trade-off between performance and energy. Comparing with the baseline CMA (non-pipelined structure), an average of 77% improvement for performance was achieved with a small power overhead. Moreover, the energy efficiency was 1461 MOPS / mW at most which was about 2× that of the baseline structure. The best pipeline depth for an arbitrary energy-performance trade-off became selectable with only 11% area overhead.

Body bias grain size exploration for a coarse grained reconfigurable accelerator

This paper explores the grain of domain size of an energy efficient coarse grained reconfigurable array called CMA (Cool Mega Array). By using Genetic Algorithm based body bias assignment method, the leakage reduction of various grain size was evaluated. As a result, a domain with 2×1 PEs achieved about 40% power reduction with a 6% area overhead.

Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB

For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator called Cool Mega Array (CMA)-SOTB is implemented by using Silicon on Thin BOX (SOTB), a new process technology developed by the Low-power Electronics Association & Project (LEAP). This chip has three voltages for controlling power and performance, supply voltage, PE-Array body bias voltage and microcontroller body bias voltage. In order to find the optimal operational point for a given requirement, a large effort for measurements and adjustments is required. This paper proposes power model for finding the optimal operation point from several measurement results. From the proposed model, the power can be estimated with 4.4% difference from the measured value on average. By using the model, the optimal source voltage and body bias voltages for PE-array and microcontroller can be obtained for a given operational frequency. Compared with the result of the exhaustive search, 37.4% of energy is saved with much small effort of measurements.

Glitch-aware variable pipeline optimization for CGRAs

Although some coarse grained reconfigurable arrays (CGRAs) have a function to unify multiple processing elements (PEs) to enhance the energy efficiency, it sometimes causes propagation of glitches widely resulting in the power increases. We propose a dynamic power model considering glitches and an optimization technique using it for CGRAs. The model aims to estimate the energy consumption from the switching counts of a PE array approximately. The model and optimization were applied to a real chip of the low power CGRA called the VPCMA (Variable Pipeline Cool Mega Array). Compared with the energy estimation with a post-layout simulation, the model could estimate it with more than 10000 times faster with smaller error from the results of the real chip measurement. The optimized pipeline structure using the proposed method achived better energy consumption compared to fixed pitch pipeline structures in most cases.

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA

Body biasing can be used to control the leakage power and the performance of transistors by changing the threshold voltage after fabrication. Especially, a new process called Silicon-On-Thin BOX (SOTB) CMOS can control the balance of these two factors. When it is applied to a Coarse-Grained Reconfigurable Array (CGRA), the leakage power can be largely reduced by controlling precisely the bias with small domain size. On the other hand, the choices on bias voltages depend on the application executed on the platform, especially its mapping. In this paper, we propose to apply a multi-objective optimization for the application mapping and the body bias control on an energy efficient CGRA called CC-SOTB (Cool Mega Array Cube-SOTB). By using an NSGA-II algorithm for the mapping exploration and Integer Linear Programming (ILP) for the body bias control optimization, we show that it is possible to achieve better power consumption results than in previous works. For instance, in the case of a domain size of 2 rows by 1 column, it is possible to achieve a power reduction ratio up to 43.25%, compared to 21.09% previously, for the studied application. This is however achieved at the cost of a bigger mapping width. Nonetheless, the exploration allows to have finer analyses about both mapping and consumption. Indeed, these promising results show that optimizing the application mapping simultaneously with the body bias control can provide more interesting results, giving deeper quantitative information about trade-off possibilities.

MuCCRA4-BB: A fine-grained body biasing capable DRP

The partitioning, implementation and in-silicon leakage evaluation of MuCCRA4-BB proved the feasibility and validity of fine-grained BB. Furthermore, it demonstrated the superiority over coarse- and chip-grained BB, minimizing FBB leakage penalty and allowing far more RBB usage in all applications and scenarios. As leakage exacerbates in smaller geometries, fine-grained BB might be an answer with sensible overhead.

Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping

Even though many optimization methods for CGRAs (Coarse-Grained Reconfigurable Architectures) have been proposed, aggressive power optimization still remains a complex problem to be solved. Moreover, the developments of these methods have mainly been proven on the basis of simulations. Therefore, the questions remains whether they can be applied for a real chip. Here, we consider a real implemented low power CGRA called CCSOTB2, and explore the possibility of the power reduction for this design. This paper proposes to use a metaheuristic method to optimize the power while considering all configurable factors of the CGRA, especially the mapping of an application. This methodology can generate mappings with their related pipeline structure and body bias control automatically. Optimized configurations to use on the real chip are obtained with this methodology and allow to measure the power consumption. The experimental results show a power reduction of 14.2% in average, when compared to a previously-used mapping method which cannot consider body bias and pipeline structure. In addition, the proposed method enables users to select a mapping from various solutions depending on performance requirement and tradeoff possibilities (e.g. throughput vs power consumption).

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Body bias control is one of the most efficient means to reduce leakage power, adjust process variation, and apply performance boost. However, such control incurs a certain power overhead that has to be reduced, especially in ultra low-power systems. In order to exploit the advantages of body bias control while guaranteeing power efficiency, an on-chip control scheme is required. Conventionally, on-chip body bias control relies on the use of digital–analog converters. However, such analog circuits require a high power supply voltage and an additional power source, resulting in a considerable power overhead and an increased system cost. In this paper, an on-chip “Digitally assisted Automatic Body-bias Tuning” (DABT) scheme for ultra low-power systems is proposed and evaluated. The proposed scheme controls the body bias voltage so as to meet the timing constraints of a given target system. Since DABT is based on “Digitally assisted” circuitries, it can decrease the power supply voltage to near-threshold region and, therefore, a significant amount of power overhead can be reduced. The proposed system is fabricated with the 65-nm silicon on thin box (SOTB) process, a fully depleted silicon on insulator technology. We demonstrate that the chip can achieve the expected functionality, even with 0.35 V of power supply voltage, and with only a few micro watts of power overhead. Moreover, the efficiency of the proposed system is evaluated with a MIPS processor, adopted as a case study. According to the obtained evaluation results, the proposed system can enable 80% of leakage reduction while maintaining the frequency required to meet the timing constraints of the adopted target MIPS processor.