Yu-Hsiung Wang

An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM

This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted.

Shrinkable triple self-aligned field-enhanced split-gate flash memory

This paper demonstrates a shrinkable triple self-aligned split-gate flash cell fabricated using a standard 0.13-/spl mu/m copper interconnect process. The approach used here to create a self-aligned structure is to form a spacer against the prior layer. Due to a higher aspect ratio when the cell pitch decreases, the profile of the spacer structure becomes sharper. This improves process control of the spacer profile and length. All the processes used here are compatible with standard logic process. The word line channel length of the cell is 0.11 /spl mu/m. It is comparable in area with a stacked-gate cell and can be less than 13F/sup 2/. The cell is erased by using poly-poly Fowler-Nordheim tunneling with a sharp floating-gate edge to increase the electric field, and is programmed by source-side injection. As a result, this cell is highly suitable for low power applications and embedded products. Characterization shows considerable program and erase speed, up to 300 K times cycling endurance, and excellent disturb margins.

Novel Cycling-induced Program Disturb of Split Gate Flash Memory

Analytical program disturb modeling of split gate flash is presented for the first time and used to estimate post-cycling time to disturb by formulating punch through current evolution with cycling. The optimized erase voltage is chosen to achieve maximum endurance based on tradeoff of erase time pushout and post-cycling program disturb. The early punch through failure mechanism of array cycling is thus understood and eliminated by new-proposed STI corner shape

Split-gate flash memory for automotive embedded applications

An embedded split-gate flash memory based on 65nm logic process technology has been developed. The design rules for split-gate flash macros testability and reliability are discussed. An automotive grade flash memory with 100K endurance, 10 years, 125°C data retention, and 1-ppm requirement has been demonstrated with a comprehensive dielectric screen methodology. Both erase time push out and data retention dominant mechanisms are thoroughly studied with intrinsic lifetime and large sample certification. An automotive embedded split-gate flash solution in 65nm technology is ready for commercialization.

High SCR design for one-transistor split-gate full-featured EEPROM

A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22 F/sup 2/ is proposed. This is in contrast to a traditional cell that requires an extra select transistor and is not area economic when compared to the new design cell. In this design, the cell adopts poly-poly Fowler-Nordheim tunneling to erase, and an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and passed 300 k program/erase (P/E) cycling test. It was found that after P/E cycling stress, the cell gains a better erase disturb immunity.

On Application of Analytical Model for Drain-Coupling Split-Gate Flash: Analytical Solution to Source-Side Injection Multilevel Programming

In this paper, we present an analytical solution for evaluating the ramped-pulse programming behaviors of the drain-coupling source-side injection split-gate flash for multilevel charge storage. Starting with the programming model, the relations of the storage charge, read current and peak lateral field to the ramped-pulse programming time are analytically expressed as functions of electrical, technological and physical parameters and agree well with experimental results. The program speed and program accuracy, including the effects of electrical bias and process variations, are analytically estimated.

Performance evaluation of field-enhanced P-channel split-gate flash memory

A p-channel split-gate Flash memory cell, employing a field-enhanced structure, is investigated in this letter. A cell with a sharp poly-tip structure is utilized to enhance the electric field, while using Fowler-Nordheim tunneling through the interpoly oxide. The cell demonstrated an erase voltage as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of /spl sim/2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300 k program/erase cycles.

Using an ammonia treatment to improve the floating-gate spacing in split-gate flash memory

In the split-gate flash memory process, during poly oxidation, the birds beak encroaches under the SiN film, especially along the poly grain boundary, and that will cause nonuniform floating-gate (FG) spacing, even bridging, which is an obstacle to cell shrinkage. In this paper, we show that employing an ammonia treatment on the poly can nitridize the poly surface, thereby avoiding birds beak bridging. After the ammonia treatment, FG spacing is quite uniform and can be improved from 0.09 to 0.03 /spl mu/m. The XPS analysis on the ammonia treated poly shows the oxynitride thickness is less than 5 nm.