Yong-Shiuan Tsair

Determination of deep ultrathin equivalent oxide thickness (EOT) from measuring flat-band C-V curve

In this letter, a novel and simple method to determine deep ultrathin oxide thickness by measuring the MOS capacitance under the flat-band condition is reported. The mechanism of this method has been profoundly studied. The results determined by this method show good agreement with those using capacitance-voltage (C-V) simulation, ellipsometer, and high-resolution transmission electromicroscopy (HRTM) analysis for thin oxides (2/spl sim/3 nm). The thickness of pure oxide extracted by this method in this experiment can be down to 1.4 nm despite the obvious C-V distortion.

Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion

Ultrathin thermally enhanced remote plasma nitrided oxides (TE-RPNO) with equivalent oxide thickness down to 1.65 nm are fabricated to investigate their leakage current reduction and boron diffusion barrier performances. A PMOSFET with TE-RPNO, compared to its conventional oxide counter-part, yields almost one order magnitude lower gate leakage current, less flatband voltage changes in high boron implantation dose or activation temperature, and shows broader process windows in the tradeoff between boron penetration and dopant activation.

A high breakdown-voltage SiCN/Si heterojunction diode for high-temperature applications

Cubic crystalline p-SiCN films are deposited on n-Si[100] substrates to form SiCN/Si heterojunction diodes (HJDs) with a rapid thermal chemical vapor deposition (RTCVD) technique. The developed SiCN/Si HJDs exhibit good rectifying properties up to 200/spl deg/C. At room temperature, the reverse breakdown voltage is more than 29 V at the leakage current density of 1.2/spl times/10/sup -4/ A/cm/sup 2/. Even at 200/spl deg/C, the typical breakdown voltage of SiCN/Si HJDs is still preserved about 5 V at the leakage current density of 1.47/spl times/10/sup -4/ A/cm/sup 2/. These properties are better than the /spl beta/-SiC on Si HJDs for high temperature applications.

High-quality ultrathin (1.6 nm) nitride/oxide stack gate dielectrics prepared by combining remote plasma nitridation and LPCVD technologies

Ultrathin nitride/oxide (N/O) gate dielectric stacks with equivalent oxide thickness of 1.6 nm have been fabricated by combining remote plasma nitridation (RPN) and low pressure chemical vapor deposition (LPCVD) technologies. NMOSFETs with these gate stacks exhibit good interface properties, improved subthreshold characteristics, low off-state currents, enhanced reliability, and about one order of magnitude reduction in gate leakage current to their oxide counterparts.

Cubic Single-Crystalline Si1 − x − y C x N y Films with Mirror Face Prepared by RTCVD

© The Electrochemical Society, Inc. [2001]. All rights reserved. Except as provided under U.S. copyright law, this work may not be reproduced, resold, distributed, or modified without the express permission of The Electrochemical Society (ECS). The archival version of this work was published in [Electrochemical and Solid-State Letters, Vol.4, No.11, pp.G91-G93].”

Novel Cycling-induced Program Disturb of Split Gate Flash Memory

Analytical program disturb modeling of split gate flash is presented for the first time and used to estimate post-cycling time to disturb by formulating punch through current evolution with cycling. The optimized erase voltage is chosen to achieve maximum endurance based on tradeoff of erase time pushout and post-cycling program disturb. The early punch through failure mechanism of array cycling is thus understood and eliminated by new-proposed STI corner shape

The 1.3–1.6 nm nitrided oxide prepared by NH3 nitridation and rapid thermal annealing for 0.1 μm and beyond CMOS technology application

Abstract High quality and high performance gate dielectrics prepared by NH 3 nitridation, with equivalent oxide thickness (EOT) down to 1.3–1.6 nm, were firstly investigated. NH 3 nitridation can effectively reduces the EOT to a lower down gate leakage current for more than one order in comparison to the control oxide with identical EOT. More significant barrier height lowering in valence band than in conduction band leads to inferior gate leakage behavior in PMOS after NH 3 nitridation. In addition, NH 3 nitrided NMOS shows a significant improvement in current drivability. But, larger V fb shift and drivability degradation were observed in PMOS. Fortunately, the most of them can be reduced with post-deposition annealing to meet the process target. The quality and reliability were also exanimated by the hysteresis, temperature and time-to-breakdown characteristics.

Effects of post-deposition treatments on ultrathin nitride/oxide gate stack prepared by RTCVD for ULSI devices

Abstract Effects of post-treatments on ultrathin nitride/oxide stacks prepared by commercial rapid thermal CVD (RTCVD) cluster tools have been investigated. Two-step post-deposition treatments (i.e., NH 3 nitridation followed by N 2 O annealing) were performed at different temperatures to study their effects on dielectric integrity and electrical characteristics. And found that the gate stack can be more stoichiometric, thinner equivalent oxide thickness (EOT) and significant reduction in leakage current simultaneously by increasing NH 3 nitridation temperature. But it suffered from slightly transconductance (G m ) degradation due to incorporation of excess nitrogen. In addition, due to interfacial modification, the improved G m can be obtained by N 2 O annealing. However, N 2 O annealing step also results in increasing EOT and degradation in gate current characteristics.

Improved current drivability and poly-gate depletion of submicron PMOSFET with poly-SiGe gate and ultra-thin nitride gate dielectric

Abstract The electrical properties of poly-SiGe gated PMOSFETs have been investigated and compared to the conventional poly-Si gated device. Both types of PMOSFETs use ultra-thin nitride gate dielectric. Poly-SiGe gated devices exhibit 10% higher inversion capacitance, improved subthreshold properties, and superior current drivability. The improvements are contributed to the suppression of the poly-gated depletion effect and the enhanced carrier mobility.

To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment

The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH/sub 3//N/sub 2/O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O/sub 2/-grown bottom oxide. In post-deposition treatment, increasing NH/sub 3/ nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N/sub 2/O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH/sub 3/ nitridation step.