Yung-Tao Lin

An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM

This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted.

Shrinkable triple self-aligned field-enhanced split-gate flash memory

This paper demonstrates a shrinkable triple self-aligned split-gate flash cell fabricated using a standard 0.13-/spl mu/m copper interconnect process. The approach used here to create a self-aligned structure is to form a spacer against the prior layer. Due to a higher aspect ratio when the cell pitch decreases, the profile of the spacer structure becomes sharper. This improves process control of the spacer profile and length. All the processes used here are compatible with standard logic process. The word line channel length of the cell is 0.11 /spl mu/m. It is comparable in area with a stacked-gate cell and can be less than 13F/sup 2/. The cell is erased by using poly-poly Fowler-Nordheim tunneling with a sharp floating-gate edge to increase the electric field, and is programmed by source-side injection. As a result, this cell is highly suitable for low power applications and embedded products. Characterization shows considerable program and erase speed, up to 300 K times cycling endurance, and excellent disturb margins.

Novel single-poly EEPROM with damascene control-gate structure

A novel single-poly EEPROM using damascene control gate (CG) structure is presented in this letter. The CG is tungsten (W) line made by a damascene process, and intergate dielectric is Al/sub 2/O/sub 3/ grown by atomic layer deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim tunneling for channel erasing. With the high dielectric constant (K) property of Al/sub 2/O/sub 3/, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-/spl kappa/ material is deposited in the back-end metallization steps without the contamination concerns on the front-end process. Therefore, this new technology is suitable for embedded application. In this letter, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention.

Novel program versus disturb window characterization for split-gate flash cell

In this letter, a new methodology for program versus disturb window characterization on split gate flash cell is presented for the first time. The window can be graphically illustrated in V/sub wl/ (word-line)-V/sub ss/ (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program bias variations. This methodology was successfully implemented in 0.18-/spl mu/m triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.

High SCR design for one-transistor split-gate full-featured EEPROM

A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22 F/sup 2/ is proposed. This is in contrast to a traditional cell that requires an extra select transistor and is not area economic when compared to the new design cell. In this design, the cell adopts poly-poly Fowler-Nordheim tunneling to erase, and an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and passed 300 k program/erase (P/E) cycling test. It was found that after P/E cycling stress, the cell gains a better erase disturb immunity.

Characteristics and improvement in hot-carrier reliability of sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors

The hot-carrier reliability of 12 V high-voltage n-channel double diffused drain metal–oxide–semiconductor (DDDMOS) field-effect transistors with various n-type double diffusion (NDD) implant dosages is investigated. A high NDD implant dosage results in a high substrate current; however, on-resistance (Ron) degradation is low. The damage location shifting toward the channel is responsible for this unexpected low Ron degradation. Technology computer-aided design (TCAD) simulation and charge pumping measurements are carried out to identify the damage location. Our analysis results reveal that an increase in NDD dosage is effective for improving the reliability of the DDDMOS field-effect transistors.

On Application of Analytical Model for Drain-Coupling Split-Gate Flash: Analytical Solution to Source-Side Injection Multilevel Programming

In this paper, we present an analytical solution for evaluating the ramped-pulse programming behaviors of the drain-coupling source-side injection split-gate flash for multilevel charge storage. Starting with the programming model, the relations of the storage charge, read current and peak lateral field to the ramped-pulse programming time are analytically expressed as functions of electrical, technological and physical parameters and agree well with experimental results. The program speed and program accuracy, including the effects of electrical bias and process variations, are analytically estimated.

New Triple Self-Aligned (SA3) Split-Gate Flash Cell with T-Shaped Source Coupling

A new triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling approach is described in this paper. This novel structure can significantly enhance coupling capacitance between the source and floating gate without increasing cell size. The enhancement can be simply modulated by an oxide-etching step. This new structure can be applied to program voltage reduction and cell size scaling. For program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6.4 V, which is characterized by a newly developed methodology for program vs disturb window characterization. For cell size scaling, comparable sort-1 and sort-2 yields are demonstrated using the new cell with a shorter floating length and a shallower source junction. To understand the relationship between source coupling ratio (SCR) and the program/erase mechanism, an insightful discussion on the program and erase mechanisms for our split-gate flash cell is also shown in this paper.

Performance evaluation of field-enhanced P-channel split-gate flash memory

A p-channel split-gate Flash memory cell, employing a field-enhanced structure, is investigated in this letter. A cell with a sharp poly-tip structure is utilized to enhance the electric field, while using Fowler-Nordheim tunneling through the interpoly oxide. The cell demonstrated an erase voltage as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of /spl sim/2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300 k program/erase cycles.

Using an ammonia treatment to improve the floating-gate spacing in split-gate flash memory

In the split-gate flash memory process, during poly oxidation, the birds beak encroaches under the SiN film, especially along the poly grain boundary, and that will cause nonuniform floating-gate (FG) spacing, even bridging, which is an obstacle to cell shrinkage. In this paper, we show that employing an ammonia treatment on the poly can nitridize the poly surface, thereby avoiding birds beak bridging. After the ammonia treatment, FG spacing is quite uniform and can be improved from 0.09 to 0.03 /spl mu/m. The XPS analysis on the ammonia treated poly shows the oxynitride thickness is less than 5 nm.