Yu-Hsuan Lin

Broadband Balanced Frequency Doublers With Fundamental Rejection Enhancement Using a Novel Compensated Marchand Balun

<?Pub Dtl?>In this paper, a novel compensation technique is proposed to improve the imbalance of a Marchand balun due to the unequal odd- and even-mode phase velocities of the coupled lines. Using this method, the fundamental rejection of the balanced doubler with the Marchand balun can be effectively enhanced. Two single-balanced doublers using the improved Marchand balun are designed, fabricated, and measured to verify the concept in CMOS processes. One doubler for 15–36-GHz possesses <formula formulatype=inline><tex Notation=TeX>

Design and Analysis of 24-GHz Active Isolator and Quasi-Circulator

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A K-Band adaptive-bias power amplifier with enhanced linearizer using 0.18-µm CMOS process

</tex></formula>10-dB conversion gain with the 3-dB bandwidth of 82.4% and the fundamental rejection of 33 dB. The other doubler for 95–150 GHz achieves <formula formulatype=inline><tex Notation=TeX>

A K-band compact fully integrated transformer power amplifier in 0.18-μm CMOS

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A low phase and gain error passive phase shifter in 90 nm CMOS for 60 GHz phase array system application

</tex></formula>7.9-dB conversion gain with the 3-dB bandwidth of 45% and the fundamental rejection of 30 dB. With the proposed compensation technique, these frequency doublers feature wide bandwidths and high fundamental rejections.

Design of a

In this paper, a new topology using the common-source amplifier, which is a unilateral component and the directional coupler, is proposed to realize an isolator without ferrite. The theory and the design procedures are presented. The performance of this isolator is comparable to those of the ferrite isolators, except for the bandwidth. The 1-dB compression point of output power (OP1dB) of the insertion loss is high due to the passive nature of the directional coupler, but the reverse isolation deteriorates with the increasing input power. The proposed 24-GHz monolithic microwave integrated circuit isolator is developed in TSMC 180-nm CMOS. Based on the proposed isolators, a quasi-circulator is designed and fabricated. Both the isolator and quasi-circulator have better OP1dB of the insertion loss than reported active isolators and quasi-circulators.

V

A new topology of power amplifier (PA) is developed in 0.18-μm CMOS. The topology adopts the adaptive bias and pre-distortion linearizer simultaneously. The design of this PA takes back-off efficiency, linear output power, and quiescent power consumption into consideration. After linearization, the proposed PA achieves 6.8% PAE at 6-dB backoff from P1dB, 14.1% PAE at OP1dB, and high linear output power 9.2 dBm with third-order intermodulation distortion (IMD3) of -40 dBc. This circuit shows good performance compared with the published PAs in 0.18-μm CMOS and suitable for high data rate transmission applications.

-Band 20-dBm Wideband Power Amplifier Using Transformer-Based Radial Power Combining in 90-nm CMOS

A K-band, 24 GHz, fully integrated transformer power amplifier (PA) is designed and fabricated in the standard 0.18-μm deep N-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration. The on-chip transformers are adopted for the power combining and impedance transformation for the matching network with a small size. The measurement results of this PA are linear gain of 15 dB, OP1dB of 18 dBm and PSAT of 23.5 dBm with power added efficiency (PAE) of 12%. Due to the small size of transformer, the size of the chip is only 0.86 × 0.56 mm2. To the authors knowledge, this PA not only demonstrates the highest output power among the CMOS PA in a 0.18-μm CMOS process, but also achieves the highest ratio of output power to chip size among the all reported K-band CMOS PAs.

A 77-GHz 2T6R Transceiver With Injection-Lock Frequency Sextupler Using 65-nm CMOS for Automotive Radar System Application

A 60 GHz passive phase shifter with low phase and amplitude error is presented in this paper. Unlike other passive phase shifter, this phase shifter consists of 2 switch type phase shifter (STPS), vector generator and vector selector to achieve 4 bit (22.5° phase resolution) and full 360° phase synthesizing. From 57-66 GHz, the measured insertion loss is 17 dB. The RMS phase and amplitude error are <; 5° and 0.5 dB, respectively, and the gain flatness is ± 0.5 dB with no dc consumption. The total chip size is 0.168 mm2. Beside, this phase shifter can operate without extra digital to analog convertor (DAC). To the authors knowledge, this phase shifter demonstrate the lowest RMS gain error and gain flatness among 60 GHz phase shifter.

A 35.7–64.2 GHz low power Miller Divider with Weak Inversion Mixer in 65 nm CMOS

This paper presents a V-band 1.2-V wideband power amplifier (PA) with a compact four-way radial power combiner in a 90-nm CMOS process. A transformer-based radial power combiner with a 1-dB insertion loss at 60 GHz and a 0.043-mm2 compact size is designed for high-output-power combining and wideband load-pull matching. This PA achieves the saturated output power (PSAT) of 20.6 dBm, the maximum power-added efficiency (PAEmax) of 20.3%, and a 20.1-dB small-signal gain (S21) at 60 GHz. The PA maintains a flat 20-dBm PSAT with PAEmax better than 17.3% within 50-64 GHz, and it has a 3-dB bandwidth (BW) of 24.5 GHz (41.8-66.3 GHz). The chip area without pads is 0.432 mm2. To the best of the authors knowledge, this V-band PA with a flat frequency response of 20-dBm PSAT presents the widest large-signal BW (50-64 GHz) compared with the reported 60-GHz CMOS high-output PAs.