Jui-Chih Kao

Millimeter-Wave CMOS Power Amplifiers With High Output Power and Wideband Performances

In this paper, we propose a design method of multi-way combining networks with impedance transformation for millimeter-wave (MMW) power amplifiers (PAs) to achieve high output power and wideband performance simultaneously in millimeter-wave frequency. Based on the proposed methodology, three power amplifiers are designed and fabricated in V-band, W-band, and D-band using 65-nm CMOS technology. With 1.2-V supply, the saturation powers of these power amplifiers are 23.2 dBm, 18 dBm and 13.2 dBm at 64 GHz, 90 GHz, and 140 GHz, with 25.1-GHz, 26-GHz, and 30-GHz 3-dB bandwidth, respectively. Compared with the published MMW amplifiers, these PAs achieve high output power and wide band performances simultaneously, and the ouput power levels is the state-of-the-art performance at these frequencies.

A 75.5-to-120.5-GHz, high-gain CMOS low-noise amplifier

In this paper, a high-gain and wideband low-noise amplifier using 65-nm CMOS process is proposed. A four-stage cascode configuration is adopted to achieve the high gain and wideband performance. With 24-mA dc current and 2-V supply voltage, the LNA not only provides gain higher than 20 dB from 75.5 GHz to 120.5 GHz, but also has a measured noise figure between 6 and 8.3 dB from 87 to 100 GHz. The output 1-dB compression power (OP1dB) is −3 dBm at 110 GHz, and the chip size is 0.55 × 0.45 mm2.

A 60-GHz Frequency Tripler With Gain and Dynamic-Range Enhancement

In this paper, a single-stage 60-GHz frequency tripler is presented with -1.1 -dB conversion gain in a 0.15-μm pseudomorphic HEMT process. When the input power backs off, unlike most of its counterparts, the conversion gain of the proposed tripler degrades very little. This feature is achieved by adjusting load impedances independently for the first and third harmonic. Besides the enhancement of the third harmonic power, substantial fundamental power is also generated without additional power consumption and is further used to drive an auxiliary diode tripler. The third harmonic power from the original field-effect transistor (FET) and the auxiliary diode tripler are combined with the conversion gain further enhanced, and the power dynamic range is also extended due to the power contributed from the auxiliary tripler. Quantitative analysis for the harmonic loading effect of the FET tripler and the bias selection for the diode tripler are conducted by using the equivalent-circuit models. The theories are verified by computer-aided design simulations and experimental results.

Design and Analysis of 24-GHz Active Isolator and Quasi-Circulator

In this paper, a new topology using the common-source amplifier, which is a unilateral component and the directional coupler, is proposed to realize an isolator without ferrite. The theory and the design procedures are presented. The performance of this isolator is comparable to those of the ferrite isolators, except for the bandwidth. The 1-dB compression point of output power (OP1dB) of the insertion loss is high due to the passive nature of the directional coupler, but the reverse isolation deteriorates with the increasing input power. The proposed 24-GHz monolithic microwave integrated circuit isolator is developed in TSMC 180-nm CMOS. Based on the proposed isolators, a quasi-circulator is designed and fabricated. Both the isolator and quasi-circulator have better OP1dB of the insertion loss than reported active isolators and quasi-circulators.

A -band High LO-to-RF Isolation Triple Cascode Mixer With Wide IF Bandwidth

A W-band triple cascode down conversion mixer using a 0.15- μm pseudomorphic high-electron mobility transistor process is proposed in this paper. Due to the utilization of modified bias topology, resistive mixing core, and IF low-pass filter, this circuit has a very wide IF bandwidth. Moreover, the triple cascode structure is used in this mixer for high local oscillator (LO)-to-RF isolation and compact chip area. The measured results illustrate that the mixer achieves 9-13-dB upper sideband conversion loss with dc-to-26-GHz IF bandwidth, and the LO-to-IF, LO-to-RF, and RF-to-IF isolation are 38, 42, and 40 dB, respectively with 5-dBm LO power at 86 GHz. When the LO power is 7 dBm at 96 GHz, the upper sideband conversion loss is 10-14 dB with dc-to-24-GHz IF bandwidth, and LO-to-IF, LO-to-RF, and RF-to-IF isolation are 29, 41.5, and 45 dB, respectively. The power consumption is 24 mW and chip area is 1 mm2.

A 60-GHz single-ended-to-differential vector sum phase shifter in CMOS for phased-array receiver

A 60-GHz vector sum phase shifter with single-ended-to-differential function for phased array receiver using 90-nm LP CMOS technology is presented. This phase shifter incorporates a four-way quadrature power divider as a vector generator with two variable gain amplifiers and a vector modulator to achieve full-360° phase synthesizing. For 4-bit operation (22.5° phase resolution) from 57–64 GHz, this phase shifter exhibits a gain error and a phase error for all the 16 states of within 2.5 dB and 11°, respectively. The RMS gain error at the two output ports are both under 1.2 dB, and the RMS phase error is under 10.5°. The RMS gain imbalance and phase imbalance between the differential outputs are under 0.8 dB and 5.2°, respectively. The average gain of one of the differential outputs at 60 GHz is −5.4 dB, and the input and output return losses are both over 10 dB. This chip consumes 34 mW from a 1.2-V supply. The chip size including all the pads is 0.96 × 0.69 mm2.

A 60 GHz Low Phase Variation Variable Gain Amplifier in 65 nm CMOS

This letter presents a 57-66 GHz low phase variation variable gain amplifier (VGA) in standard RF 65 nm CMOS process with a chip area of 0.25 mm2. The phase compensation is achieved by using the different trends of phase between current-steering and splitting-cascade topologies. This VGA achieves the phase variation lower than 7° with 33 dB gain control range (GCR). The 3 dB bandwidth is from 50 to 70 GHz with 21 dB peak gain.

A 57-66 GHz Vector Sum Phase Shifter with Low Phase/Amplitude Error Using a Wilkinson Power Divider with LHTL/RHTL Elements

Abstract-A vector sum phase shifter (VSPS) using 90 nm CMOS process is presented. The VSPS can synthesize any amplitude and phase at certain frequencies, so the phase and amplitude error can be minimized. The proposed VSPS using a wideband Wilkinson power divider with left-hand transmission line (LHTL)/right-hand transmission line (RHTL) elements to achieve low phase error over a wide bandwidth. The measured RMS phase and amplitude error are under 5.1° and 0.5 dB over 57 -66 GHz, respectively. The average amplitude is about -5 dB. The dc power consumption is less than 15.6 mW (13 mA, 1.2 V). The chip area is 0.315 mm2 without pads. To the authors knowledge, this phase shifter demonstrates the lowest RMS phase and amplitude error over a wide bandwidth among the reported phase shifters around 60 GHz in CMOS processes.

A 57–64 GHz low-phase-variation variable-gain amplifier

A 57–64 GHz current-steering variable-gain amplifier (VGA) with low-phase-variation characteristics is presented in this paper. The phase analysis of current-steering topology reveals the effect of the phase compensation capacitor. The proposed VGA achieves peak gain of 13–15 dB from 57–67 GHz, and the phase variation is lower than 6.6° within 15.5-dB gain control range (GCR) in the desired band. The dc power consumption is 36 mW from 2-V supply voltage.

A 77-GHz 2T6R Transceiver With Injection-Lock Frequency Sextupler Using 65-nm CMOS for Automotive Radar System Application

In this paper, a CMOS multichannel transceiver (TRX) is proposed for angular identification in automotive car radar applications. Two transmitters (TXs) and six receivers (RXs) are placed on the same die using 65-nm CMOS technology with chip size 3.5 × 3 mm2. To generate a millimeter-wave (MMW) frequency-modulated continuous-wave signal, an injection-lock frequency sextupler cascaded a 1-to-8 Wilkinson power dividing network with wideband isolation is designed as the LO-chain to convert external source from 12.5-13.7 to 75-82.2 GHz for both the TXs and RXs. Each TX achieves above 11-dBm output power and the RXs achieve 30-dB conversion gain from 75 to 82 GHz, and the total power dissipation of whole chip is 1.43 W. Compared with other published multichannel TRXs in silicon germanium (SiGe) process, this paper demonstrates compatible performances and the potential of multichannel TRX using CMOS for MMW automotive car radar application.