Yu-Liang Wu

A dual-mode built-in self-test technique for capacitive MEMS devices

A built-in self-test (BIST) scheme which partitions the fixed (instead of movable) capacitance plates of a capacitive MEMS device is proposed. The BIST technique divides the fixed capacitance plate(s) at each side of the movable microstructure into three portions: one for electrostatic activation and the other two equal portions for capacitance sensing. Due to such partitioning, the BIST technique can be applied to surface-, bulk-micromachined MEMS devices and other technologies. Further, sensitivity and symmetry BIST methods based on this partitioning are also introduced. The combination of both BIST modes covers a larger defect set, thus a robust testing for the device can be expected. The BIST technique is verified by three typical capacitive MEMS devices. Simulation results show that the proposed technique is an effective BIST solution for various capacitive MEMS devices.

A cost-effective scan architecture for scan testing with non-scan test power and test application cost

A new scan architecture is proposed for full scan designed circuits. Scan flip-flops are grouped together if they do not have any common successors. This technique produces no new redundant faults. Scan flip-flops in the same group have the same values in all test vectors. All scan flip-flop groups form a scan forest, where each primary input drives the root of one scan tree. Test application time and test power based on the proposed scan forest architecture can be reduced drastically while pin overhead and delay overhead should be the same as that of conventional scan design. It is shown that test application cost and test power with the proposed scan forest architecture can be reduced to the level of non-scan design circuits.

Graph based analysis of 2-D FPGA routing

In this paper, we study the two-dimensional FPGA, Xilinx-like routing architectures and present the first known computational complexity results for them. The routing problem is formulated as a two-dimensional interval packing problem and is proved to be NP-complete with or without doglegs. Next, we consider other routing structures obtained from the industrial one by arbitrarily changing switch box connection topology while maintaining the same connection flexibility. There is an exponentially large number of such routing structures. We further prove that there does not exist a better routing architecture among the members of this large domain. In addition, we prove that there is no constant bound on the mapping ratio of a track number required by a detailed routing to a global routing channel density for the studied architectures. Finally, we show two directions of changing the routing architectures which yield polynomial time mapping solutions and constant bounded mapping ratios. Our theoretical analysis is intended to give some insight to, and understanding of this new routing problems fundamental properties.

A fast graph-based alternative wiring scheme for Boolean networks

Alternative wiring techniques have been shown to be very useful for many EDA problems. The currently used rewiring techniques are mainly ATPG based. In this paper, we study the approach of applying purely graph based local pattern search methods in locating alternative wires. The method searches minimal graph patterns containing alternative wires that are limited to 2 edges distant from the target wire. The experimental result shows that this scheme is very fast and has the advantage of searching both the nearby forward and backward alternative wires easily. The overall number of alternative wires searched is quite comparable (104%), compared to the forward search only RAMBO version, and the CPU time is 200 times faster. We also illustrate its usage, among many others, by a simple coupling with the SIS algebraic operations and let this rewiring tool serve as a netlist-perturbing engine for logic minimization. The coupling scheme shows a further reduction of 8.5% in area compared to applying algebraic script alone, with a nearly negligible CPU overhead spent in rewiring.

On optimum switch box designs for 2-D FPGAs

An FPGA switch box is said to be universal (hyper-universal) if it can detailed route all possible surrounding 2-pin (multi-pin) net topologies satisfying the global routing density constraints. A switch box is optimum if it is hyper-universal and the switches inside is minimum. It has been shown that if the net topology is restricted to 2-pin nets, then a 2-D (4-way) switch box can be built to be universal with only 6Wswitches, whereWis the global routing channel density. As the routing resource is relatively expensive in FPGA chips, study of the optimum switch box designs is clearly a topic with theoretical and commercial value of reducing silicon cost. A previous work has constructed a formal mathematical model of this optimum design problem for switch boxes with arbitrary dimensions, and gave a scheme to produce hyper-universal designs with less than 6.7W switches for 4-way FPGA switch boxes. In this paper, we will further investigate this most common 4-way switch box case, and will give new theoretical results followed by extensive experimental justification. The results seem to be quite attractive. We show that such an optimum switch box can be built with a very low number of additional switches beyond 6W for todays practical range of lowWs (e.g. just 6Wplus 1 or 2 additional switches forWs up to 7). Even for arbitrary largeWs, the bound can be shown to be under 6.34W. To make experimental comparison, we run todays published best FPGA router VPR on large benchmarks for the popular Disjoint structure and our proposed designs. The results are quite encouraging.

Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing

We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a different optimization target are designed. By applying one algorithm first and then switching to the other when the first one approaches its decaying stage, the undesired effect can be significantly reduced and thus better results are produced. On the tested MCNC and industry benchmarks, in addition to our very low segment consumption the total number of tracks used by our scheme is 37% less than a published conventional maze router and 22% less than the best known 2-step global/detailed router [4,5]. Our results show that complicated multi-objective problems could be effectively attacked by coupling low complexity algorithms that traverse the solution space in orthogonal directions. This idea is applicable on both algorithmic and architectural optimization approaches [7].

Further improve circuit partitioning using GBAW logic perturbation techniques

Efficient circuit partitioning is becoming more and more important as the size of modern circuits keeps increasing. Conventionally, circuit partitioning is solved without altering the circuit by modeling the circuit as a hypergraph for the ease of applying graph algorithms. However, there is room for further improvement on even optimal hypergraph partitioning results, if logic information can be applied for circuit perturbation. Such logic transformation based partitioning techniques are relatively less addressed. In this paper, we present a powerful multiway partitioning technique which applies efficient logic rewiring techniques for further improvement over already superior hypergraph partitioning results. The approach can integrate with any graph partitioner. We perform experiments on two-, three-, and four-way partitionings for MCNC benchmark circuits whose physical and logical information are both available. Our experimental results show that this partitioning approach is very powerful. For example, it can achieve a further 12.3% reduction in cut size upon already excellent pure graph partitioner (hMetis) results on two-way partitioning with an area penalty of only 0.34%. The outperforming results demonstrate the usefulness of this new partitioning technique.

Routing for array-type FPGA's

In this paper, the routing problem for two-dimensional (2-D) field programmable gate arrays of a Xilinx-like architecture is studied. We first propose an efficient one-step router that makes use of the main characteristics of the architecture. Then we propose an improved approach of coupling two greedy heuristics designed to avoid an undesired decaying effect, a dramatically degenerated router performance on the near completion stages. This phenomenon is commonly observed on results produced by the conventional deterministic routing strategies using a single optimization cost function. Consequently, our results are significantly improved on both the number of routing tracks and routing segments by just applying low-complexity algorithms. On the tested MCNC and industrial benchmarks, the total number of tracks used by the best known two-step global/detailed router is 28% more than that used by our proposed method.

On optimal hyperuniversal and rearrangeable switch box designs

This paper explores theories on designing optimal multipoint interconnection structures, and proposes a simple switch box design scheme which can be directly applied to field programmable gate arrays (FPGAs), switch box designs, and communication switching network designs. We present a new hyperuniversal switch box designs with four sides and W terminals on each side, which is routable for every multipin net-routing requirement. This new design is proved to be optimum for W = 1, ..., 5 and close to optimum for W /spl ges/ 6 with 6.3 W switches. We also give a formal analysis and extensive benchmark experiments on routability comparisons between todays most well-known FPGA switch boxes like disjoint switch blocks (Xilinx XC4000 Type), Wiltons switch blocks, Universal switch blocks, and our Hyperuniversal switch boxes. We apply the design scheme to rearrangeable switching network designs targeting for applications of connecting multiple terminals (e.g., teleconferencing). Simply using a /spl kappa/-sided hyperuniversal switch block with a W /spl times/ W crossbar attached to each side, one can build a three-stage one-sided polygonal switching network capable of realizing every multipoint connection requirement on kW terminals. Besides, due to the fine-grained decomposition property of our design scheme, the new switch box designs are highly scalable and simple on physical layout and routing algorithm implementations.

Design and analysis of self-repairable MEMS accelerometer

In this paper, a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n + m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. If any of the working module in the main device is found faulty, the control circuit will replace it with a good redundant module. In this way, the faulty device can be self-repaired through redundancy. The sensitivity loss due to device modularization can be well compensated by different design alternatives. The yield model for MEMS redundancy repair is developed. The simulation results show that the BISR (built-in self-repair) design leads to effective yield increase compared to nonBISR design, especially for a moderate nonBISR yield. By implementing the fault tolerance feature into MEMS devices, the yield as well as the reliability of a MEMS device implemented in a SoC can be improved.