Yi Diao

ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells

To maintain a lower re-masking cost, Engineering Change Order (ECO) using pre-placed spare cells for buffer insertion and gate sizing has been shown to be practical for fixing timing violating paths (ECO paths). However, in the previously known best scheme DCP [1, 2], re-routings are done with each path optimized according to its surrounding available spare cells without considering potential exchanges with neighboring active cells, and spare cell arbitration between competing ECO paths are less addressed. Besides, the extra flexibility for allowing logic restructuring was not exploited. In this work, we develop a framework harnessing the following more flexible strategies to make the usage of spare cells for ECO timing optimization more powerful: (1) a negotiation based re-routing scheme yielding a more global view in solving resource competition arbitration; (2) an extended gate sizing operation to allow exchanges of active gates with spare gates of different function types through equivalent logic re-structuring. Our experiments upon MCNC and ITC benchmarks with highly injected timing violations show that compared to DCP, our newly proposed framework can cut down the average total negative slack (TNS) by 50% and reduce the number of unsolved ECO paths by 31%.

Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates)

There are situations (e.g. for reverse engineering or formal verification) circuit designers would need to extract complicated arithmetic circuitry deeply embedded inside a fully synthesized (or manually touched) million-gate flattened netlist without the knowing of module boundary and IO positions. Besides not knowing the IO and boundary, a formal verification task like comparing two netlists implementing (4A+3B)×C and 4A×C+3B×C respectively is quite challenging for it is an NP-Complete Circuit-SAT problem too. To tackle this problem, we propose a novel Complementary Greedy Coupling (CGC) approach coupling reverse engineering and SAT techniques together for each of them only performs well at proving equality or inequality respectively. The scheme is quite powerful, being able to handle commonly implemented arithmetic modules (Ripple/CLA adders, MUX, various multipliers and their combinations) with runtime complexity nearly linear to the number of circuit gates. For an example, our scheme can verify two 32-bit multipliers (Wallace vs Modified-Booth) within 5 seconds (regardless of their equality or inequality), while running SAT alone might take 1010 centuries. We compared our tool Easy-LEC with the two on market commercial tools using the 182 open benchmarks posted for ICCAD CAD Contest 2014. Besides running at least 400 to 1400 times faster, our scheme also solves 32% to 45% more cases (93% vs 61% or 48%).

A universal macro block mapping scheme for arithmetic circuits

A macro block is a functional unit that can be re-used in circuit designs. The problem of general macro block mapping is to identify such embedded parts, whose I/O signals are unknown, from the netlist that may have been optimized in various ways. The mapping results can then be used to ease the functional verification process or for replacement by more advanced intellectual property (IP) macros. In the past literatures, the mapping problem is mostly limited to the identification of a single adder or multiplier with I/O signals given, which is already NP-hard. However, in todays typical arithmetic circuits (like digital signal processing (DSP) applications), it is not unusual to have combinations of arithmetic operators implemented as macro blocks for performance gain. To solve this new practical mapping problem, we propose a flow to identify and build a forest of one-bit-adder trees using structural information and formal verification techniques, followed by algorithms that locate macro boundaries and I/O signal orders. Experimental results show that our algorithm is highly practical and scalable. It is capable of identifying any combinations of arbitrary adders and multipliers such as (a + b) × c and a × b + c × d +e × f, where each operand is a multi-bit constant or variable. Most of the benchmarks in ICCAD 2013 CAD Contest [1] can be well handled by our algorithm.

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire

In a deep sub-micron technology era where wiring delays are more dominating, being able to remove any undesirable signal wire (e.g. too long, hardly routable, or highly delay-violating) with chip functionality unchanged should be quite useful for circuit optimizations. Rewiring is a logic transformation technique through which a target wire can be removed by adding its alternative logics with functionality intact. However, normally the rewiring rate (percentage of original circuit wires being removable by rewiring) for most techniques is only 30% to 40% for optimized circuits in the past. A recently proposed error cancellation based rewiring scheme FECR has finally achieved a breaking rewiring rate of 95% however with an impractical algorithm complexity of (O(n5)). In this paper we propose a Delete and Correct (DaC) rewiring in terms that a target wire is deleted first then the circuit is corrected by adding just one or two new wires. This DaC technique, besides being much more efficient (O(n2)), can also achieve a near complete rewiring rate (over 95%) even for fully optimized circuits. Experimentally, the runtime is largely reduced by 32 times compared to FECR. As any logic gate can also be removed through exercising this DaC operation repeatedly, perhaps some originally involved cell-based logic synthesis flow could now be rebuilt atop this simple, atomic (and universal) wiring-based logic operation with better performance predictability.

To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO

During the EDA process, a design may be tampered directly by dishonest engineers (or “industry spy”), or may be tampered indirectly through the use of malicious modules from a third party Intellectual Property (3PIP) block vendor. During integration and fabrication, the chips may also be tampered by untrusted system integrator or even foundry. Particularly for high-end commercial or classified military chips, Hardware Trojan (HT) Detect-Locate-and-Mask (DL&M) is crucially necessary so as to make sure a design is produced exactly as the original specification (golden). Our objectives are (1) to detect any functionality difference which might be caused by bugs or HTs, (2) to locate/output the difference circuitry to correct the bugs or to investigate the tampering intention or purpose, and (3) to “kill” (mask) the HTs by restoring the chips functionality back to golden with a minimum circuitry change. Besides blocking the plotted damage in an early stage and pointing the spy source by revealing the HT intention, the masking circuit revision must also be minimized to avoid affecting the chip performance (timing) too much. In this paper, we propose a scheme that integrates reverse engineering, formal verification, functional ECO, and logic rewiring to detect, locate and mask Hardware Trojans with minimized cost. This formal verification based scheme can guarantee catching 100% of the hidden combinational circuit HTs and can handle multiple HTs (no number limit) automatically in one run. Some techniques within our scheme won the first places of the CAD Contests at ICCAD 2012, 2013, and 2014 [1-3].

Boolean Circuit Rewiring: Bridging Logical and Physical Designs

Demonstrates techniques which will allow rewiring rates of over 95%, enabling adoption of deep sub-micron chips for industrial applications Logic synthesis is an essential part of the modern digital IC design process in semi-conductor industry. This book discusses a logic synthesis technique called rewiring and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in todays semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire-based transformations. This book introduces the automatic test pattern generation (ATPG)-based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs. Unique comprehensive coverage of semiconductor rewiring techniques written by leading researchers in the field Provides complete coverage of rewiring from an introductory to intermediate level Rewiring is explained as a flexible technique for Boolean logic synthesis, introducing the concept of Boolean circuit transformation and testing, with examples Readers can directly apply the described techniques to real-world VLSI design issues Focuses on the automatic test pattern generation (ATPG) based rewiring methods although some non-ATPG based rewiring methods such as graph based alternative wiring (GBAW), and set of pairs of functions to be distinguished (SPFD) based rewiring are also discussed A valuable resource for researchers and postgraduate students in VLSI and SoC design, as well as digital design engineers, EDA software developers, and design automation experts that specialize in the synthesis and optimization of logical circuits.

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield

A macro-fault is defined as a group of signal faults such that the errors induced cannot be observed unless two or more faults (either permanent or temporary) in the group happen simultaneously. Since adding a redundant (alternative) wire for an existing (target) wire can mask some certain faults of these two wires mutually, a macro-fault can be formed by redundant wire addition. The faults that are dominated by or equivalent to the masked faults are also included in the macro-fault. As the feature size of integrated circuit technologies continue to scale down, manufacturing fault-free chips is getting more difficult and fault tolerance techniques will become more critical. In the past, redundancy has been adopted for memory for improving fault tolerance. For critical circuit components, even the costly triple modular redundancy techniques have to be applied. In this work, we study the implications of our new fault model, macro-fault, on the potential impact on fault tolerance and manufacturing yield. Based on the findings, a heuristic approach based on redundant wire addition is designed for improving fault tolerance. The approach can be incorporated with other fault tolerance techniques to form a hierarchical cross-layer fault tolerance scheme.