Yu-Pin Han
STMicroelectronics
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Publication
Featured researches published by Yu-Pin Han.
IEEE Journal of Solid-state Circuits | 1989
Fu-Tai Liou; Yu-Pin Han; Frank Randolph Bryant; Mehdi Zamanian
A 0.8- mu m polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (+or-0.2) mu m are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8- mu m full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail. >
Archive | 1987
Fu-Tai Liou; Yu-Pin Han; Frank Randolph Bryant
Archive | 1995
Tsiu Chiu Chan; Yu-Pin Han; Elmer Henry Guritz
Archive | 1988
Frank Randolph Bryant; Yu-Pin Han; Fu-Tai Liou; Tsiu Chiu Chan
Archive | 1982
Yu-Pin Han; Tsiu Chiu Chan
Archive | 1996
Tsiu Chiu Chan; Yu-Pin Han; Elmer Henry Guritz; Richard A. Blanchard
Archive | 1985
Tsiu C. Chan; Yu-Pin Han
Archive | 1992
Frank Randolph Bryant; Yu-Pin Han; Fu-Tai Liou
Archive | 1988
Yu-Pin Han; Fu-Tai Liou; Frank Randolph Bryant
Archive | 1986
Tsiu C. Chan; Yu-Pin Han