Frank Randolph Bryant

A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

A 0.8- mu m polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (+or-0.2) mu m are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8- mu m full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail. >

Transmission electron microscopy characterization of defects resulting from the polycrystalline silicon buffered local oxidation of silicon isolation process

Polybuffered LOCOS is used for isolation of active devices in submicron integrated circuits. Many papers have reported on the defects resulting from this process. We report, for the first time, on the structure and composition of these defects and relate the defects to a phenomenon similar to the traditional Kooi effect [E. Kooi, J. G. van Lierop, and J. A. Apples, J. Electrochem. Soc. 123, 1117 (1976)].

A Manufacturable 0.7amu;m Triple Metal Technology For High Density And High Performance ASIC Applications

A high performance manufacturable 0.7pm triple metal technology has been developed on SGS-Thomson’s HCMOS4 twin-well CMOS process. Improvements in metal processes to obtain reliable barrier layer and excellent step coverage make it possible to use A1 alloy in all three metal interconnects. Good reliabilities on device hot carrier degradation, metal electromigration and dielectric breakdown were achieved. The process has been succcssful in fabricating a gate array product with greater than 30% yield for 220Kmi12 die size.

A 0.5 mu m diode load 4 Mb SRAM technology using double-level Al plug metal process

A 4 Mb SRAM technology using 0.5 mu m transistors with 12.5 nm gate oxide, TiN local interconnection, polysilicon diode loads, and Al plug double level metallization is described. The use of diode load yields T Omega polysilicon resistors whose values are nearly independent of geometry. Complete filling of 0.6 mu m contacts and vias are obtained using Al plug metallization.<<ETX>>

A 0.8 mu m CMOS technology for high performance ASIC memory and channelless gate array

A generic 0.8- mu m, polycide-gate, double-layer metal CMOS technology with twelve masking steps for next-generation memories and gate arrays has been developed. Key design rules and technology features are given. An I-line stepper is used for fine line definition down to the 0.7- mu m region. The technology has been demonstrated with a full CMOS 16 K SRAM (static random-access memory) circuit. POP-SILO isolation, 175-A gate oxide, Ta polycide gate material, halo LDD (lightly doped drain) n and p devices, TiN/TiSi/sub 2/ contact and barrier metal, partial etchback SOG (spin-on-glass) planarization, and Al/Ti metal systems provide high performance and reliable process technology.<<ETX>>