Yuan-Ho Chen

Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG

We present a new reseeding-mixing method to extend the system period length and to enhance the statistical properties of a chaos-based logistic map pseudo random number generator (PRNG). The reseeding method removes the short periods of the digitized logistic map and the mixing method extends the system period length to 2253 by “xoring” with a DX generator. When implemented in the TSMC 0.18- μm 1P6M CMOS process, the new reseeding-mixing PRNG (RM-PRNG) attains the best throughput rate of 6.4 Gb/s compared with other nonlinear PRNGs. In addition, the generated random sequences pass the NIST SP 800-22 statistical tests including ratio test and U-value test.

High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree

In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.

A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications

In this brief, a probabilistic estimation bias (PEB) circuit for a fixed-width twos-complement Booth multiplier is proposed. The proposed PEB circuit is derived from theoretical computation, instead of exhaustive simulations and heuristic compensation strategies that tend to introduce curve-fitting errors and exponential-grown simulation time. Consequently, the proposed PEB circuit provides a smaller area and a lower truncation error compared with existing works. Implemented in an 8 × 8 2-D discrete cosine transform (DCT) core, the DCT core using the proposed PEB Booth multiplier improves the peak signal-to-noise ratio by 17 dB with only a 2% area penalty compared with the direct-truncated method.

A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers

In this paper, a single compensation formula of adaptive conditional-probability estimator (ACPE) applied to fixed-width Booth multiplier is proposed. Based on the conditional-probability theory, the ACPE can be easily applied to large length Booth multipliers (such as 32-bit or larger) for achieving a higher accuracy performance. To consider the trade-off between accuracy and area cost, the ACPE provides varying column information to adjust the accuracy with respect to system requirements. The 16-bit ACPE Booth multiplier with w = 3 reduces 28.9% silicon area with only 0.39 dB signal-to-noise ratio (SNR) loss when compared with post-truncated (P-T) Booth multiplier. Furthermore, the ACPE Booth multipliers are applied to two-dimensional (2-D) discrete cosine transform (DCT) to evaluate the system performance. Implemented in a TSMC 0.18 CMOS process, the DCT core with ACPE (w = 3) can save 14.3% area cost with only 0.48 dB peak-signal-to-noise-ratio (PSNR) penalty compared to P-T method.

A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy

In this paper, a spatial and time scheduling strategy, called the space-time scheduling (STS) strategy, that achieves high image resolutions in real-time systems is proposed. The proposed spatial scheduling strategy includes the ability to choose the distributed arithmetic (DA)-precision bit length, a hardware sharing architecture that reduces the hardware cost, and the proposed time scheduling strategy arranges different dimensional computations in that it can calculate first-dimensional and second-dimensional transformations simultaneously in single 1-D discrete cosine transform (DCT) core to reach a hardware utilization of 100%. The DA-precision bit length is chosen as 9 bits instead of the traditional 12 bits based on test image simulations. In addition, the proposed hardware sharing architecture employs a binary signed-digit DA architecture that enables the arithmetic resources to be shared during the four time slots. For this reason, the proposed 2-D DCT core achieves high accuracy with a small area and a high throughput rate and is verified using a TSMC 0.18-μm 1P6M CMOS process chip implementation. Measurement results show that the core has a latency of 84 clock cycles with a 52 dB peak-signal-to-noise-ratio and is operated at 167 MHz with 15.8 K gate counts.

Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias

In this paper, a closed form of compensation function for fixed-width Booth multipliers using generalized probabilistic estimation bias (GPEB) is proposed. Based on the probabilistic estimation from the truncation part, the GPEB circuit can be easily built according to the proposed systematic steps. The GPEB fixed-width multipliers with variable-correction outperform the existing compensation circuits in reducing error. An 8 × 8 GPEB Booth multiplier improves more than 88% on the reduction of absolute average error compared with the traditional direct truncation (D-T) multiplier, and more than 32% area savings is obtained in the GPEB Booth multiplier compared with posttrun cation (P-T) Booth multiplier. By the same power consumption, the GPEB Booth multipliers can achieve higher accuracy than the existing works. Besides, considering power efficiency with accuracy, the proposed GPEB Booth multiplier has the most power-efficiency compared with other methods. Furthermore, the GPEB Booth multipliers are implemented in the circuit of two-dimensional discrete cosine transform (DCT). Compared with traditional Booth multipliers applications, the proposed 2-D DCT cores can reduce about 18% area cost with the penalty of only 0.8 dB peak signal-to-noise ratio (PSNR). Consequently, the Booth multiplier utilizing area-efficiency, power-efficiency, and high-accuracy is achieved using the proposed GPEB.

Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.

High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic

This paper proposes a low-cost high-throughput multistandard transform (MST) core, which can support MPEG-1/2/4 (8 × 8), H.264 (8 × 8, 4 × 4), and VC-1 (8 × 8, 8 × 4, 4 × 8, 4 × 4) transforms. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. This achieves a 44.5% reduction in adders in the proposed MST, compared with the direct implementation method. With eight parallel computation paths, the proposed MST core has an eightfold operation frequency throughput rate. Measurements show that the proposed CSDA-MST core achieves a high-throughput rate of 1.28 G-pels/s, supporting the (4928 × 2048@24 Hz) digital cinema or ultrahigh resolution format. This is possible only with 30 k gate counts when implemented in a TSMC 0.18- μm CMOS process. The CSDA-MST core thus achieves a high-throughput rate supporting multistandard transformations at low cost.

A statistical error-compensated Booth multipliers and its DCT applications

In this paper a statistical error compensation (SEC) method for fixed-width Booth multipliers is proposed. According to the statistical simulation for the truncation part, the adaptive compensated biases based on the truncated factors for different bit-width compensated circuit are made up. For the 8×8 fixed-width Booth multiplier as an example, the proposed method achieves higher accuracy comparison with previous works under the same area cost. Furthermore, the proposed SEC Booth multiplier is implemented in two-dimensional (2-D) discrete cosine transform (DCT). Compared to traditional Booth multipliers applications, the proposed 2-D DCT core can reduce 22% area cost with almost 2 dB peak signal-to-noise ratio (PSNR) penalty. Therefore, the proposed multiplier has a low hardware cost achieving high accuracy designs.

An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability

This brief proposes an accuracy-adjustment fixed-width Booth multiplier that compensates the truncation error using a multilevel conditional probability (MLCP) estimator and derives a closed form for various bit widths L and column information w. Compared with the exhaustive simulations strategy, the proposed MLCP estimator substantially reduces simulation time and easily adjusts accuracy based on mathematical derivations. Unlike previous conditional-probability methods, the proposed MLCP uses entire nonzero code, namely MLCP, to estimate the truncation error and achieve higher accuracy levels. Furthermore, the simple and small MLCP compensated circuit is proposed in this brief. The results of this brief show that the proposed MLCP Booth multipliers achieve low-cost high-accuracy performance.