Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Yuanyuan Pu is active.

Publication


Featured researches published by Yuanyuan Pu.


international conference on electronic packaging technology | 2009

Effects of nitrogen on wettability and reliability of lead-free solder in reflow soldering

Mingzhi Dong; Yuming Wang; Jian Cai; Tao Feng; Yuanyuan Pu

Electronic assembly technology is in the transition from traditional Tin-lead to lead-free, which leading to challenge in many aspects. It is accepted that nitrogen can improve the wettability and reliability of lead-free solders; however, few systemic researches have been reported. In this work, the spreading ratio of Sn-Ag-Cu solder was measured through spreading tests under different atmosphere conditions. When oxygen concentration was 1000ppm and reflow temperature was 5°C lower than non-inerted reflow, the spreading ratio of Sn-Ag-Cu solder was comparable with the non-inerted one. PCBs and SMT components were assembled in nitrogen-inerted (oxygen concentration: 1000ppm) and non-inerted reflow. The nitrogen-inerted reflow temperature was 5°C lower. Pull and shear tests were employed as the evaluation of the soldering. Random vibration test and isothermal aging test were conducted as reliability evaluation. The morphology of the interfacial intermetallic compounds (IMCs) during wetting and reliability tests were studied as well.


international conference on electronic packaging technology | 2012

A quick turn packaging solution and its application

Han Guo; Jian Cai; Yuanyuan Pu; Yu Chen; Qian Wang; Zhi Deng; Jing Jiang; Lingwen Kong

With the rapid development of semiconductor industry, reducing time-to-market and cost become very important for manufacturing companies during product development. Generally, customized substrate is required for each chip design in IC packaging. However, design and manufacture of customized substrate usually take several weeks, which significantly impact cycle time of product development. To solve the problem, some companies offer Ceramic Open Tooled Package (COTP), which is very expensive and challenging for assembly. In this paper, organic-based Multi-Program Package (MPP) is proposed and analyzed as an efficient and low cost solution to accelerate packaging development, especially for pilot run of packaging. Universality is a typical feature of MPP. MPP provides a quick turn solution for chips with different designs, such as different functions, die sizes, numbers of 110, distributions of die pads, through a series of specially designed substrates. The MPP substrates can be designed and manufactured in advance. Then customers choose suitable MPP solution according to their chip design and package requirements. By proper modification of bonding diagram, the product will be packaged through standard assembly process. In this way, customers like IC design houses may have a flexible choice to realize their pilot run. In this paper, an example of real MPP application, MPP121, is introduced. MPP121 adopted Plastic Ball Grid Array (PBGA) package structure. The substrate design is applied for nine packages with different die size and 110 number. Electrical and reliability test results showed an excellent chip performance after package.


international conference on electronic packaging technology | 2010

A BGA package design of a read-out ASIC for GEM imaging detector

Yuanyuan Pu; Jian Cai; Zhi Deng; Yulan Li; Xiaocui Zheng; Shuidi Wang

The ASIC involved in this paper is a read-out FET array for GEM imaging detector. In the ASIC, 4 (rows) × 8 (columns) units are implemented in an area of 2.5 mm × 2.5 mm. The ASIC is designed with a minimum readout cycle of 100 ns. As a read-out array for imaging detector, the package should be assembled in array form too, thus limits the package size. This paper would introduce the package design for this read-out ASIC, in which the substrate design is mainly focused on. The design limited in specific demands obeys the JEDEC design guide for fine-pitch BGA. The substrate is a 4-layer BT board, with two signal layers and two planes. For the package, designed ball size is 0.3mm. And the package height without attached solder balls is 1.06 +/−0.04 mm. After the process of substrate design and manufacture, die attach, wire bonding, molding, dicing and manual ball attachment, the package has been realized. The practical test for the package has been partially finished. Also the SI simulation is given out to compare with the results practical test brings out. With the results of SI simulation and practical test, the electrical performance of the designed package was evaluated.


Archive | 2012

Output-end fan-out type flip-chip packaging structure without baseplate

Jian Cai; Qian Wang; Yuanyuan Pu; Jingyi Chen; Shuidi Wang


Archive | 2011

Chip size package structure of flip chip without base plate

Jian Cai; Qian Wang; Yuanyuan Pu; Jingyi Chen; Shuidi Wang


Archive | 2011

Wafer level making method with flip-chip bump structure

Jian Cai; Shuidi Wang; Qian Wang; Yuanyuan Pu; Jingyi Chen


Archive | 2011

Fan-out-type output end flip chip packaging structure without base plate

Jian Cai; Qian Wang; Yuanyuan Pu; Jingyi Chen; Shuidi Wang


Archive | 2012

Universal package substrate, package structure and package method

Jian Cai; Yuanyuan Pu; Qian Wang; Han Guo


Archive | 2012

Method for implanting RFID (radio frequency identification) signal into PCB (printed circuit board)

Jian Cai; Yuanyuan Pu; Qian Wang; Shuidi Wang; Songliang Jia


Archive | 2012

Method for designing general packaging substrate

Jian Cai; Yuanyuan Pu; Qian Wang; Han Guo

Collaboration


Dive into the Yuanyuan Pu's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge