Yudan Pi

Preliminary validation of entransy-based thermal management for 3D IC

With the development of IC technology, 3 dimensional (3D) architecture (3D IC) has been proposed as a new solution to realize high density and low interconnect delay. Despite of the advance in device performance, 3D IC brings forth many new challenges such as reliability, yield, and so on. Meanwhile, heat dissipation inside a 3D structure becomes more difficult because of the thinner stack, the higher power density and the larger quantity of inter-layer dielectrics, usually with a low thermal conductivity. Thermal management of 3D IC requires suitable optimization parameter to evaluate the heat transfer performance, especially in the automatic thermal-aware routing. This paper examined the effectiveness of the entransy, a new concept in the modern heat transfer, as an evaluation criterion. Numerical results showed that the tendencies of the entransy dissipation and the maximum temperature are consistent, which preliminarily verified its applicability in thermal management of 3D-IC.

A Fast and Low Computation Consumption Model for System-Level Thermal Management in 3D IC

With the rapid increment of the power density and the introduction of vertical stack, heat dissipation has become a challenge issue. Thermal-aware placement thereby attracts more and more attentions for 3D IC. Meanwhile, as the keep-going scaling-down of IC, a huge computation consumption was caused by the large scale span. In this paper, an equivalent anisotropic thermal conductivity model was introduced to low down the computation consumption caused by the huge feature size difference. Correctness of this model was verified and the deviation from a full-scale simulation was less than 20%. By applying this model, thermal distribution of a designed 3D IC with 1566 TSVs and 80504 hot-spots was obtained with the total computation time of about 24 minutes in a regular personal computer.

Microfluidic Cooling for Distributed Hot-Spots

2.5D/3D Stacking technique offers a promising solution to extend the Moore Law, meanwhile also leads to a serious heat dissipation challenge. Micro-channels based microfluidic cooling, embedded in the interposer or different layers of 3D IC, targeting at i nserting heat sink into each layer, can considerably shorten the heat transfer path and thereby enhance the heat dissipation. It is worth noting that because of the spreading resistance, even with the same micro-channel structure, the effective thermal dissipation capability shows different on varies hot-spot size. In this paper, a micro-fluidic cooling chip with different-sized hot-spots was fabricated to investigate the influence of h ot-spot characteristics on the cooling ability of the embedded micro-channel. Relationship between temperature and flow rate was experimentally measured as engineering guide in the thermal design of IC with embedded microfluidic cooling.

Equivalent Thermal Conductivity Model Based Full Scale Numerical Simulation for Thermal Management in Fan-Out Packages

Exploring along the road of More Moore with integration degree increasing significantly, different wafer level 3-D technologies are developed facing various circumstances. Thermal issue has become an important concern in IC designing and manufacturing. Fan-out wafer level package (FOWLP), as one of the most popular packaging trends lately, compared to high cost through silicon via (TSV) based 3D integration method, requires system level thermal management. Full scale numerical simulation as a critical procedure is facing huge difficulties, such as huge structure size variation, huge thermal properties variation, in-plane and off-plane displacement, etc. Equivalent thermal conductivity model (ETCM) based full scale numerical simulation for thermal management, which has already been applied to TSV based 3-D ICs with computation consumption significantly decreased, is applied to Fan-out packages in this paper. Equivalent and anisotropic thermal conductivity is calculated and modified concerning FOWLP structure and material thermal properties. A chip-first face-up fan-out package with 100 pads and 100 bumps is modeled and simulated, with mesh elements number drops from 874836 to 174810. With more than 80% computation consumption saved, less than 2% difference in total temperature rise is obtained compared with detail simulation.

A full chip scale numerical simulation method for thermal management of 3D IC

Thermal issue is becoming more and more serious when integrated circuits (IC) further explores along the road of More Moore with dramatic increments of integration degree and power density. Thermal management, including thermal design, modeling, and optimization, has been an important concern in the system-level design of 3D IC. Current thermal modeling for a system level 3D IC design usually relies on a simplified thermal resistance network, which requires trade-offs between the model complexity and the simulation accuracy. Comparing to traditional thermal resistance based model, finite element simulation can provide a more accurate simulation for the thermal management of 3D IC. However, a full chip scale numerical simulation is still lack as an unacceptable huge grid number is unavoidable to deal with the geometric size mismatch existed in a 3D IC. Moreover, current finite element method based numerical simulation tools have no direct supports for the thermal management of 3D IC, since the placement design usually consists a complex data structure from a 3D IC. A method to bridge the finite element method and the 3D IC placement is introduced in this work. The whole bridge process includes placement data structure extraction, 3D IC system model generation, structure, mesh, solver configuration, calculation, and post data analysis. A full chip scale numerical simulation was demonstrated based the present bridge method along with the recently reported equivalent thermal conductivity simplified model.

An accurate calculation method on thermal effectiveness of TSV and wire

With the rapid increment of the power density and decrement of chip size, thermal management has become a critical problem in three-dimensional integrated circuit (3D IC). Through-silicon-via (TSV) is widely used to alleviate thermal problems thanks to its high thermal conductivity. However, thermal effectiveness of TSV in the thermal management varies in different situations. In this paper, based on a simplified thermal resistance calculation of heat dissipation path constructed by TSV and Cu wire, thermal effectiveness of TSV is defined for thermal management. The simplified model is verified by a full scale numerical simulation. The present thermal effectiveness shows potential in engineering guidelines for TSV and Cu wire design in thermal-aware 3D IC floorplanning.

Investigations of silicon wafer bonding using thin Al and Sn films for heterogeneous integration

Metallic wafer bonding has emerged as a key technology for microelectronics and MEMS. The Si wafers with Al metallization film on surface are bonded by applying Sn film as intermediate layer, aiming at the application of heterogeneous integration. Averaged shear strength of 9.9 MPa is realized at bonding temperature as low as 280°C with bonding time as short as 3 minutes under the bonding pressure of 0.25 MPa. Interface microstructure and fracture surface analysis were carried out to understand the underlying mechanism.

Groove structure for stress releasing around TSV

Through silicon via (TSV) is one of the most significant techniques in microelectronic packaging. In 3 dimensional integrated circuit (3D IC), TSV brings great performance improvement and high density device integration. Meanwhile, the usage of copper in TSV causes serious thermal stress issue, which considerably affects the device performance and reliability. This paper proposed a unique structure to release TSV-induced stress. Numerical simulation was used to study the stress distribution around the TSV and optimize the geometric parameters, including the depth, width and position of the proposed stress-releasing groove.