Yufeng Jin

MEMS vacuum packaging technology and applications

Vacuum packaging is essential for various kinds of microelectromechanical system (MEMS) devices for enhancing the performance and reliability. This paper presents our works on research on vacuum packaging of MEMS devices. A hermetical sealing technique has been developed, which involves the processes of anodic bonding for silicon and glass wafers with imperfect interface, adhesive bonding, glass frit bonding and silicon-to-gold eutectic bonding. Vacuum maintenance has been achieved by applying evaporable and nonevaporable getter films in the packaging process. A specific helium leak detector with bombing system is introduced, which can monitor the deformation of micro diaphragms and conduct leak detection for MEMS structures.

Studies on a micro combustor for gas turbine engines

The design, fabrication and characterization of a silicon-based micro combustor for gas turbine engines are reported in this paper. The micro combustor consists of seven-layer microstructures fabricated from silicon wafers, and it adopts a novel fuel–air recirculation channel for extending gas flow path. Numerical simulations based on computational fluid dynamics (CFD) demonstrate a guideline for selecting parameters during combustor operation and indicate that the flame temperature inside the combustor reaches 1700 K. Experimental investigations have demonstrated that a stable combustion can be sustained inside the micro combustor. The highest temperature measured at the edge of the combustor exit has reached 1700 K, and the average temperature recorded near the exit ranges from 1200 K to 1600 K.

A parylene-filled-trench technique for thermal isolation in silicon-based microdevices

Microdevices prepared in a silicon substrate have been widely used in versatile fields due to the matured silicon-based microfabrication technique and the excellent physical properties of silicon material. However, the high thermal conductivity of silicon restricts its application in most thermal microdevices, especially devices comprising different temperature zones. In this work, a parylene-filled-trench technique was optimized to realize high-quality thermal isolation in silicon-based microdevices. Parylene C, a heat transfer barricading material, was deposited on parallel high-aspect-ratio trenches, which surrounded the isolated target zones. After removing the remnant silicon beneath the trenches by deep reactive ion etching from the back side, a high-quality heat transfer barrier was obtained. By using narrow trenches, only 5 ?m thick parylene was required for a complete filling, which facilitated multi-layer interconnection thereafter. The parylene filling performance inside the high-aspect-ratio trench was optimized by two approaches: multiple etch?deposition cycling and trench profile controlling. A 4 ? 6 array, in which each unit was kept at a constant temperature and was well thermally isolated individually, was achieved on a silicon substrate by using the present parylene-filled-trench technique. The preliminary experimental results indicated that the present parylene-filled-trench structure exhibited excellent thermal isolation performance, with a very low power requirement of 0.134 mW (K mm2)?1 for heating the isolated silicon unit and a high thermal isolation efficiency of 72.5% between two adjacent units. Accompanied with high-quality isolation performance, the microdevices embedded the present parylene-filled-trench structure to retain a strong mechanical connection larger than 400 kPa between two isolated zones, which is very important for a high-reliability-required micro-electro-mechanical-system (MEMS) device. Considering its room-temperature processing essence, the present parylene-filled-trench technique is believed to be a promising isolation method in the post-complementary metal oxide semiconductor MEMS integration.

Zr/V/Fe thick film for vacuum packaging of MEMS

An approach to maintain vacuum in microelectromechanical systems (MEMS) by integrating the MEMS fabrication process with getter material preparation is presented in this paper. The coating process for a thick film of getter material on silicon and glass wafers, the two commonly used substrates in MEMS fabrication and package, was investigated in detail. The getter material consists of a powder mixture of zirconium, vanadium and iron, which features high sorption capacity to active gases such as H2, O2, N2, CO and H2O vapour. Various kinds of patterned non-evaporable getter (NEG) thick films with thickness from 50 µm to 400 µm were fabricated to investigate the solutions for different MEMS applications. The activation temperature of the thick NEG films was investigated. Fundamental properties of the NEG films were examined, such as the adhesive strength, higher than 119 N cm−2, of the NEG film to Si substrate and the sorption capacity, 4.68 × 106 Pa l m−2, of the coated getter material. The coating of NEG thick film on the inner surface of MEMS pressure sensor illustrates the applicability of the technique in vacuum maintenance of MEMS devices.

HERMETIC PACKAGING OF MEMS WITH THICK ELECTRODES BY SILICON-GLASS ANODIC BONDING

Thick electrodes, which are widely used in micro-electro-mechanical system (MEMS) devices, create serious surface imperfection and would result in a low-quality bond or even debonding. In this work, the influence of electrode thickness on hermetic sealing was investigated. Two approaches to realise hermetic sealing via anodic bonding of silicon to glass with thick electrodes are presented. Embedded electrode is one method in which metal was deposited on shallow trench etched on the surface of wafers and planarisation of bonding surface was performed with a Chemical Mechanical Polishing (CMP) process. Another approach, called vertical via electrode method, is to form vertical electrodes through vias by deposition and patterning of metal film.

High-aspect-ratio fabrications of micro journal air bearings for micro gas turbine engine

In micro fabricated gas turbine engine, a micro journal air bearing is used to offer high speed and low wear operations. Fabrication of such a journal bearing is a critical challenge since the clearance of the bearing is only several micrometers with aspect ratio of more than 20. This paper reports on the fabrication of ultra-high aspect ratio micro journal air bearing using ICP DRIE (inductively coupled plasma deep reactive ion etching) process. The process parameters that resulted in bowed and tpaered journal bearing were investigated to improve the profile of the etched journal bearing. Micro journal bearings with sidewall verticality of almost 90° were obtained.

Data Transfer Performance Analysis and Enhancement of Critical 3D Interconnects in a 3D SiP Based on Communication Channel Modeling Methodology

Electromagnetic (EM) and circuit modeling are the prevailing practices for the anticipation and extraction of data transfer performances of 3D interconnects in a system-in-package (SiP). In comparison, this paper proposes a more abstract and cost-efficient evaluation method and an enhancement method thereof from the perspective of network information theory and communication channel modeling. Firstly, as the basis of the modeling, effects of non-idealities along data path and interferences are investigated by EM and circuit modeling and simulations, adopting typical 3D data links and their neighboring data lines as examples. Then, a channel model covering the data link of interest, based on network information theory, is established to anticipate its bit error rate (BER) as a key performance index up to a bit rate of 10Gbps, which is demonstrated to be intuitive and time-efficient. Eventually, a performance enhancement measure is proposed utilizing channel coding. The effectiveness and overhead of 2 codes with error correction capabilities are evaluated against un-coded scenario, realizing an BER enhancement from 10exp(-1) to 10exp(-5). In comparison, most conventional measures are more physical ones like shielding and complex error-proof transceivers configurations, which are often prohibitive in SiP scenario due to cost or overhead reasons. Thus, the method proposed may not only be a cost-efficient supplement to existing design methodologies but as more intuitive and insightful one on a higher level of design.

Influence of Viscoelastic Underfill on Thermal Mechanical Reliability of a 3-D-TSV Stack by Simulation

In this paper, we focus on how viscoelastic underfill influences the thermal mechanical reliability of a 3-D through-silicon-via (3-D-TSV) stack. The Williams–Landel–Ferry equation and relaxation of the modulus in the Prony series are used to describe the viscoelastic properties of underfill in detail. The 3-D-TSV stack consists of a four-layer die stack, a silicon interposer, a printed circuit board, TSVs, microbumps, and solder balls. Simulation results show that, with underfill applied, chip warpage is worse and the residual stress of the microbumps is increased. Therefore, a design suggestion is proposed where underfill with a lower coefficient of thermal expansion is preferred in 3-D-TSV stacks for applications undergoing heavy thermal cycles. In terms of simulation accuracy, the simulation is compared with the simplified treatment where underfill is considered completely elastic. We conclude that defining the viscoelasticity properties is more relevant for underfill than elasticity.

Evaluation and Optimization of Thermo-Mechanical Reliability of a TSV-Based 3D MEMS

This paper focuses on the thermo-mechanical reliability of a 3D-TSV MEMS in which cap layer and MEMS micro-structure layer is vertically interconnected and bonded by TSVs/micro-bumps and a sear ring. Geometrical parameters of the TSV structure and the seal ring are optimized first before the global model simulation. Smaller thickness of bottom TSV Cu and smaller opening size of silicon oxide layer are preferred in terms of thermo-mechanical reliability and electrical reliability. Quarter circular arc corner turning of radius 50μm decreases shear stress by at most 43.7% and peeling stress by at most 55.4% when compared with any other corner turning. In the end, the optimized structure parameters are introduced into the global model reliability simulation to verify the feasibility of the 3D-TSV MEMS.

Process Development and Characterization for Integrating Microchannel into TSV Interposer

Thermal management is a key challenge for TSV (through-silicon-via) enabled integrated three-dimensional microsystem and integrated microchannel cooling is believed as a promising technology because of high inner-chip cooling efficiency. In this paper, a compatible process is presented for integrating microchannel into TSV interposer and three typical types of integrated microchannel are implemented based on the developed process. And the three types of microchannel design evaluated in term of cooling efficiency under typical thermal loads by simulation results. Furthermore, electrical path composed of TSVs is modeled and simulated, coupling influence of integrated microchannel on electrical performance of the TSV path is analyzed.