Zuo-Min Tsai

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P₁ _dB of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P₁ _dB of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the authors knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.

Millimeter-Wave CMOS Power Amplifiers With High Output Power and Wideband Performances

In this paper, we propose a design method of multi-way combining networks with impedance transformation for millimeter-wave (MMW) power amplifiers (PAs) to achieve high output power and wideband performance simultaneously in millimeter-wave frequency. Based on the proposed methodology, three power amplifiers are designed and fabricated in V-band, W-band, and D-band using 65-nm CMOS technology. With 1.2-V supply, the saturation powers of these power amplifiers are 23.2 dBm, 18 dBm and 13.2 dBm at 64 GHz, 90 GHz, and 140 GHz, with 25.1-GHz, 26-GHz, and 30-GHz 3-dB bandwidth, respectively. Compared with the published MMW amplifiers, these PAs achieve high output power and wide band performances simultaneously, and the ouput power levels is the state-of-the-art performance at these frequencies.

A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors

A noise optimization formulation for a CMOS low-noise amplifier (LNA) with on-chip low-Q inductors is presented, which incorporates the series resistances of the on-chip low-Q inductors into the noise optimization procedure explicitly. A 10-GHz LNA is designed and implemented in a standard mixed-signal/RF bulk 0.18-/spl mu/m CMOS technology based on this formulation. The measurement results, with a power gain of 11.25 dB and a noise figure (NF) of 2.9 dB, show the lowest NF among the LNAs using bulk 0.18-/spl mu/m CMOS at this frequency.

A High-Range-Accuracy and High-Sensitivity Harmonic Radar Using Pulse Pseudorandom Code for Bee Searching

This paper presents a 9.4/18.8-GHz harmonic radar to investigate the behavior of bees with colony collapse disorder. The challenges of using harmonic radar for bee searching include the requirements of high range accuracy and high sensitivity. A new harmonic radar using the pseudorandom code positioning technique to simultaneously achieve high range accuracy and high sensitivity is proposed. This study also proposes a new method to cancel the local leakage to further improve sensitivity. To realize the transponder, a compact antenna is designed using the topology characteristics of the composite right/left-handed transmission-line concept. The measured sensitivity of the transceiver is -120 dBm, which is 27 dB lower than the noise level. Field testing results demonstrate a 60-m detection range within 1-m distance error with 1.75-W transmitting power. The significant improvement of the sensitivity and the range accuracy reveal the advantages of applying the code-positioning technique to the harmonic radar.

Analysis and Design of Bandpass Single-Pole–Double-Throw FET Filter-Integrated Switches

This paper proposes a method to integrate a single-pole - double-throw (SPDT) switch and a quarter-wavelength bandpass filter. A 1-GHz SPDT hybrid switch and a 60-GHz pseudomorphic HEMT monolithic-microwave integrated-circuit SPDT switch with 30% fractional bandwidth are demonstrated. The 1-GHz SPDT switch achieves 1.5-dB insertion loss and 20-dB isolation at center frequency. For the 60-GHz SPDT switch, the measured insertion loss is lower than 2.5 dB and the isolation is higher than 27 dB. The low insertion loss and high isolation show that no performance is degraded when integrating the filter function. The analysis of the power performance is also described. Using the device dc-IV curves, the power compression point can be predicted.

Design and Analysis of Stacked Power Amplifier in Series-Input and Series-Output Configuration

The stacked-device power-combining technique is a proven method to increase the output power and load impedance of a power amplifier (PA) simultaneously. The series-input configuration is physically realizable for multicell stacked device configuration in monolithic circuits. The series-input and series-output stack configuration is rigorously analyzed and proven to increase both the input impedance and output impedance simultaneously, easing the matching circuit designs in high PAs. The effects of asymmetry of the input feed and amplifier cells due to distributed effects and process variation on the performance of the stack amplifier are discussed. A four-cell HBT amplifier operating at 5-6 GHz is demonstrated to validate the circuit concept.

Integrated Circuits of a PFC Controller for Interleaved Critical-Mode Boost Converters

Boost converters operated in critical mode can achieve high efficiency, while they have some limitations, such as high current ripple, high component rating and low power application. Thus, this paper proposes integrated circuits (IC) of a powerfactor corrector (PFC) controller for interleaved critical-mode boost converters. The proposed PFC control IC can achieve the features of interleaving function, zero voltage switching, wide input voltage range and wide output load range. Simulated results obtained from two-phase boost converters with the proposed PFC IC have verified the features and control schemes of the proposed controller.

Phase-Noise Reduction of

A low phase-noise X-band push-push oscillator using proposed feedback topology is presented in this paper. The oscillator core was implemented in a 0.18-mum CMOS process. By using a power splitter and a delay path in the feedback loop connecting the output and current source of the oscillator, a part of the oscillator output power injects to the oscillator itself. With the proper phase delay in the feedback loop and high transconductance of the current source, a low phase-noise oscillator is achieved. The amplitude stability and phase stability are analyzed, the phenomena of the phase-noise reductions are derived, and the device-size selections of the oscillator are investigated. The time-variant function, impulse sensitivity function, is also adopted to analyze the phase-noise reductions of the second-harmonic self-injected push-push oscillator. These theories are verified by the experiments. This self-injected push-push oscillator achieves low phase noise of -120.1 dBc/Hz at 1-MHz offset from the 9.6-GHz carrier. The power consumption is 13.8 mW from a 1.0-V supply voltage. The figure-of-merit of the oscillator is -188.3 dBc/Hz. It is also the first attempt to analyze the second-harmonic self-injected push-push oscillator

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A new circuit topology, named ring-coupled quad for millimeter-wave voltage controlled oscillator (VCO) design, is proposed. The proposed circuit topology provides higher open loop voltage gain than conventional cross-coupled pair. The layout of the proposed ring-coupled quad is fully symmetric without additional interconnection lines. A 90-GHz VCO using 90-nm CMOS process is implemented with this ring-coupled quad. This 90-GHz oscillator demonstrates a 2.5-GHz tuning range and higher than -20dBm output power. The proposed ring-coupled quad is suitable for the realization of high frequency VCOs