Yue Kuo

PECVD Silicon Nitride as a Gate Dielectric for Amorphous Silicon Thin Film Transistor Process and Device Performance

Plasma-enhanced chemical vapor deposited (PECVD) silicon nitride is a popular gate dielectric for the inverted, staggered thin film transistors (TFTs). In this paper, two subjects have been studied: the low temperature, i.e., 250 o C, silicon nitride SiN x deposition process, and the TFT performance based on various SiNs dielectric films. For the PECVD SiN x process, a general mechanism, which includes the coexistence of deposition and etching reactions, is presented. Data from the plasma-phase chemistry, ion bombardment, and film characteristics are used to examine the above model. For TFT applications, device characteristics such as the field effect mobility, the threshold voltage, and the subthreshold slope were shown to be influenced by the deposition process. A relation between the threshold voltage and the nitride characteristics has been observed. The threshold voltage is the lowest when the SiN x layer has a refractive index in the range of 1.85 to 1.90. The exact reason is unknown, but it is possible that the SiN x charge-trapping density is the lowest when the film has a certain ratio of SiH to NH

Reactive Ion Etching of Sputter Deposited Tantalum Oxide and Its Etch Selectivity to Tantalum

Reactive ion etching of the sputter deposited tantalum oxide has been studied. Process parameters that affect the etch rate, such as the power, pressure, and temperature, were investigated in a wide range of conditions. Etch selectivities between tantalum and tantalum oxide in various processes have been examined. By exchanging one F atom in the CF 4 molecule or one Cl atom in the CF 3 Cl molecule with one H atom, we can reverse the etch selectivity. Structures of the etched surfaces were characterized with the electron spectroscope for chemical analysis

Electrical and Physical Characterization of Zirconium-Doped Tantalum Oxide Thin Films

Thin films of zirconium-doped tantalum oxide (Zr-doped TaO x ) deposited by reactive sputtering were studied in an effort to replace silicon dioxide (SiO 2 ) as the gate dielectric material for future metal-oxide-semiconductor devices. Influences of process parameters, such as Zr concentration, postdeposition annealing temperature, and film thickness, on the films electrical and physical characteristics were investigated. The lightly Zr-doped film (15 nm thick) showed a low current density, e.g., 1.27 X 10 -9 A/cm 2 at -1 MV/cm in the accumulation regime. The current conduction mechanism of the Zr-doped TaO x films was analyzed and compared with mechanisms of Poole-Frenkel and Schottky emissions. In comparison with pure tantalum oxide (TaO x ) and zirconium oxide (ZrO,) films, the Zr-doped TaO x films had higher dielectric constants. A high-temperature annealing step reduced the films hysteresis and fixed charge density. The interface layer composition changed from SiO x to zirconium silicate (Zr x Si y O) when the Zr concentration in the film was increased. The binding energies of Ta 4f, Zr 3d, and O Is of the bulk shifted to lower values as the Zr concentration increased due to the charge transfer among elements. In summary, the Zr-doped TaO x films showed many advantages over pure TaO x and ZrO y films for the gate dielectric application.

Sub 2 nm Thick Zirconium Doped Hafnium Oxide High-K Gate Dielectrics

Zr-doped HfOx high-k gate dielectric films with TiN gate electrode were sputter deposited on 1 nm SiO2 or SiOxNy interface layer. Electrical properties including the equivalent oxide thickness, flat band voltage, interface state density, and the oxide charge trapped density of the MOS capacitors were investigated with respect to fabrication parameters such as Zr doping condition, post deposition annealing ambient, and type of bottom interface layer. Excellent electrical properties were obtained for films deposited at low sputtering powers. An equivalent oxide thickness of 1.7 nm was achieved for Zr-doped HfOx on a 1 nm SiO2 interface. The leakage current is four orders of magnitude lower than that of the SiO2 film. The magnitude and polarity of the flat band voltage is influenced by the high-k film deposition method, the dopant concentration, and the post deposition annealing condition. With the same SiOxNy interface layer, the Zr-doped film has a lower leakage current and a smaller interface density of states than the undoped film.

Hafnium-doped tantalum oxide high-k dielectrics with sub-2 nm equivalent oxide thickness

Hafnium-doped tantalum oxide high dielectric constant films, i.e., with an equivalent oxide thickness as low as 1.3 nm, have been prepared and studied. The doped film has a bulk layer dielectric constant greater than 28 and an interface layer (formed with silicon substrate) dielectric constant greater than 8. The doping process changed the bulk and the interface layer structures as well as energy band gaps. The postdeposition annealing atmosphere showed major impacts on material and electrical properties. The new high-k material is a viable gate dielectric film for future metal-oxide-semiconductor transistors.

Dielectric relaxation and breakdown detection of doped tantalum oxide high-k thin films

While TaO/sub x/, HfO/sub x/, ZrO/sub x/, Hf-doped TaO/sub x/, and Zr-doped TaO/sub x/ thin films are promising high-k gate dielectric candidates, their intrinsic reliability has not yet been investigated. In this paper, the authors examine some fundamental reliability aspects of these high-k films through ramp voltage stress testing. By studying dielectric relaxation and analyzing the transient conductivity, the breakdown mode of the tested high-k film is identified; a sensitive method of breakdown detection in ramped voltage tests is proposed and investigated.

POLYCRYSTALLINE SILICON FORMATION BY PULSED RAPID THERMAL ANNEALING OF AMORPHOUS SILICON

A method of forming polycrystalline silicon (polysilicon) from amorphous silicon in several seconds is presented in this letter. This solid‐phase crystallization process was carried out with the pulsed rapid thermal annealing method using a metal as the seed. The crystal‐growth process was monitored with an optical microscope and the polysilicon structure was confirmed by a micro‐Raman shift measurement. Polysilicon film within a 30‐micrometer channel was formed using 3 pulses of 1‐s 800 °C heating/5‐s cooling. It took more than 13 h using a 500 °C furnace annealing method to form polysilicon film within a 12‐micrometer channel. Since the substrate is only exposed to the high temperature for a very short period of time, heat effects in the substrate are minimized. This method has the potential for use in the fabrication of small geometry devices, such as thin film transistors, on large‐area, low temperature glass substrates.

Thin-Film Transistor and Ultra-Large Scale Integrated Circuit: Competition or Collaboration

Thin-film transistor (TFT) and ultra-large scale integrated circuit (ULSIC) have been compared and discussed with respect to the development history, technology trends, and applications. Detailed issues on materials, processes, and devices in the large-area TFT array fabrication and nano-size metal–oxide–semiconductor field effect transistors (MOSFETs) composed ULSIC on large wafers were also examined. The TFT fabrication processes were originally derived from ULSIC. However, there are many unique large-area processes and theories developed during the study of the TFT array fabrication, which can greatly benefit the future large wafer ULSIC production process. Although their future applications will be in different areas, there are opportunities that TFTs can be integrated into ULSIC products to enhance the functions and performance.

Etch mechanism in the low refractive index silicon nitride plasma‐enhanced chemical vapor deposition process

In this letter the author reports a generalized mechanism for the plasma‐enhanced chemical vapor deposition silicon nitride process which includes simultaneous surface deposition and etching reactions. The etching mechanism is caused by the hydrogen plasma in combination with the high plasma potential. For each deposition versus power or refractive index versus power curve there is a critical point which is determined by the critical power Wcritical. When the power is lower than Wcritical, the process can be explained by conventional deposition mechanisms. When the power is higher than Wcritical, the hydrogen etching mechanisms becomes important. Wcritical depends on other process parameters such as the composition of the feeding stream. Experimental results confirmed the hydrogen etching mechanism, which is selective.

Hafnium-Doped Tantalum Oxide High-k Gate Dielectrics

Physical and electrical properties of hafnium-doped tantalum oxide thin films were studied. The doping process affects the structures, composition, thickness, dielectric constant, charges, and leakage current density of both the bulk film and the interface layer. Compared with the undoped film, the lightly doped film exhibited improved dielectric properties, such as a higher dielectric constant, a smaller fixed charge density, a larger dielectric strength, and a lower leakage current. The postdeposition annealing process condition, such as temperature and time, also influences the high-k films dielectric properties. In summary, the hafnium-doped tantalum oxide film is a promising high-k gate dielectric material for future metal-oxide-semiconductor devices.