Yuejin Hou

Revisit to the finite element modeling of electromigration for narrow interconnects

Electromigration (EM) is an important reliability concern in ultralarge-scale integration interconnects. A refined EM model based on a driving force approach is proposed in this work. The distribution of atomic flux divergence is computed by an finite element method to predict the void nucleation site in interconnects. It is demonstrated that the proposed model is more accurate than the conventional counterpart for narrow interconnects. The validity of the proposed model is verified through the study of the reservoir effect in EM. The predicted critical reservoir length agrees well with the reported values.

Stress-induced voiding study in integrated circuit interconnects

An analytical equation for an ultralarge-scale integration interconnect lifetime due to stress-induced voiding (SIV) is derived from the energy perspective. It is shown that the SIV lifetime is strongly dependent on the passivation quality at the cap layer/interconnect interface, the confinement effect by the surrounding materials to the interconnects, and the available diffusion paths in the interconnects. Contrary to the traditional power-law creep model, we find that the temperature exponent in SIV lifetime formulation is determined by the available diffusion paths for the interconnect atoms and the interconnect geometries. The critical temperature for the SIV is found to be independent of passivation integrity and dielectric confinement effect. Actual stress-free temperature (SFT) during the SIV process is also found to be different from the dielectric/cap layer deposition temperature or the final annealing temperature of the metallization, and it can be evaluated analytically once the activation energy, temperature exponent and critical temperature are determined experimentally. The smaller actual SFT indicates that a strong stress relaxation occurs before the high temperature storage test. Our results show that our SIV lifetime model can be used to predict the SIV lifetime in nano-interconnects.

Lifetime modeling for stress-induced voiding in integrated circuit interconnections

By considering the stress-induced voiding (SIV) as a result of strain energy relief in the presence of flaws, an analytical lifetime model for SIV is derived from the energy perspective. The SIV lifetime is strongly dependent on the passivation integrity of the cap layer, effective bulk modulus of the interconnect system, diffusivities of the interconnect atoms in the dominant diffusion paths, stress free temperature, and temperature of the interconnection. The calculated SIV lifetime and the critical temperature are found to be consistent with the experimental values.

Comparison of stress-induced voiding phenomena in copper line-via structures with different dielectric materials

The package level stress-induced voiding (SIV) test of Cu dual-damascene line?via structures is performed. Two different dielectrics, undoped silica glass (USG) and carbon doped oxide (CDO), are used in this work. After 1344 h of high temperature storage test, the resistance drift of USG interconnects is found to be much smaller than that of CDO interconnects and voids are located at the bottom of the via for both USG and CDO interconnects. However, horizontal voids grown along the via bottom is observed for USG interconnects, whilst voids are found to grow vertically along the via sidewall for CDO interconnects. The phenomena are explained using finite element analysis in this work, and the observed poor SIV performance for CDO interconnects is also explained. With this finite element analysis, the implications of different low-k dielectrics on SIV reliability are discussed.

Size effect in Cu nano-interconnects and its implication on electromigration

With the interconnect dimensions approaching the length of the mean free path (MFP) of the electron, size effects are becoming important. This is manifested in the increase of the resistivity for nano-interconnects. This change in the electrical properties will pose new challenges in the EM performance for Cu nano-interconnects.

Blech Effect in Cu Interconnects with Oxide and Low-k Dielectrics

This paper investigates the mechanism of the temperature dependence of the Blech product for both the Cu/oxide and Cu/low-k interconnections. Using finite element modeling (FEM), we demonstrate that Blech product should be temperature dependent at high temperature if the inelastic behavior of Cu is considered. This inelastic behavior has not been taken into consideration in the previous works. The simulated Blech product is found to be consistent with the literature reported values.

Electromigration in width transition copper interconnect

Abstract Electromigration (EM) experiments are conducted for submicron dual damascene copper interconnects with width transition. The direction of electron flow (from narrow-to-wide segment and wide-to-narrow segment) and the ratio of lengths (e.g. ratio of narrow-to-wide segment lengths) are found to be significant factors in determining the life-time of such interconnects. About 69% shorter EM life-time is obtained for the case of electron flow from narrow-to-wide segment, and thus to avoid over estimation of EM life-time of such interconnect system, the direction of the electron flow should be chosen appropriately in the reliability assessment. On the other hand, it is found that the width transition location is not the failure site, and finite element model is presented to explain the experimental findings.

Development of Physics-Based Modeling for ULSI Interconnections Failure Mechanisms: Electromigration and Stress-Induced Voiding

In this chapter, we present a comprehensive review on the physics-based modeling of EM phenomena in ULSI interconnections over the last three decades. In the evolution of the physics-based modeling, some aspects of the physics are dropped for simplification, and some are added to accommodate new understanding on the EM physics as well as for the new development of the interconnect technology. With the continuous change in the metallization system and materials, the aspects of physics that have been dropped may become important again, and new physics might also occur with these changes in metallization system. Here, we re-examine the justification of dropping or adding various physical aspects in the EM modeling during their evolution and their implications on the future interconnect system.

Finite Element Method for Stress-Induced Voiding

With the basic physics of stress-induced voiding (SIV) introduced in Chap. 2, the detailed finite element modeling of the mechanisms of SIV in Cu interconnect will be described here. The understanding of the voiding mechanism through the modeling can certainly shed light on the future design and process improvement of the multilevel interconnect structures. The most widely used commercial finite element software for finite element analysis is ANSYS or ABAQUS.

Finite Element Method for Dielectric Reliability

The effective dielectric constant (K eff ) is a concept to characterize the integrated working permittivity of a structure consisting of various dielectrics of different dielectric constants.