Zhenghao Gan

Preparation and characterization of copper oxide thin films deposited by filtered cathodic vacuum arc

Copper oxide thin films deposited on Si (100) by a filtered cathodic vacuum arc with and without substrate bias have been studied by atomic force microscopy, x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and Raman spectroscopy. The results show that the substrate bias significantly affects the surface morphology, crystalline phases and texture. In the film deposited without bias, two phases—cupric oxide (CuO) and cuprous oxide (Cu2O)—coexist as cross-evidenced by XRD, XPS and Raman analyses, whereas CuO is dominant concurrent with CuO (020) texture in the film deposited with bias. The film deposited with bias exhibits a more uniform and clearer surface morphology although both kinds of films are very smooth. Some explanations are given as well.

Dynamic study of the physical processes in the intrinsic line electromigration of deep-submicron copper and aluminum interconnects

Various physical mechanisms are involved in an electromigration (EM) process occurring in metal thin film. These mechanisms are electron-wind force induced migration, thermomigration due to temperature gradient, stressmigration due to stress gradient, and surface migration due to surface tension in the case where free surface is available. In this work, a finite element model combining all the aforementioned massflow processes was developed to study the behaviors of these physical mechanisms and their interactions in an EM process for both Al and Cu interconnects. The simulation results show that the intrinsic EM damage in Al is mainly driven by the electron-wind force, and thus the electron-wind force induced flux divergence is the dominant cause of Al EM failure. On the other hand, the intrinsic EM damage in Cu is driven initially by the thermomigration, and the electron-wind force dominates the EM failure only at a latter stage. This shows that the early stage of void growth in Cu interconnects is more prone to thermomigration than Al.

Intrinsic mechanical properties of diamond-like carbon thin films deposited by filtered cathodic vacuum arc

The mechanical properties—Young’s modulus (E) and hardness (H)—of diamond-like carbon (DLC) thin films deposited on p2+ Si (100) by filtered cathodic vacuum arc with different substrate bias voltage have been studied by nanoindentation measurement, where the substrate effect is included. Their intrinsic properties [including E,H, and yield strength (Y)] without the substrate effect are then derived by finite element analysis. The results show that the intrinsic mechanical properties of the DLC thin films are not affected by the film thickness, but significantly affected by change of sp3 bonding fraction caused by varied substrate bias. An empirical relationship among E, Y, and H for DLC thin films has been built, where E, Y, and H are intrinsic properties of DLC thin films. It is also confirmed that, as an empirical rule, the measured H could be used to represent its intrinsic value when the indentation depth is limited to 10% of the film thickness. However, the measured E with the substrate effect does n...

Determination of the dice forward I–V characteristics of a power diode from a packaged device and its applications

Abstract The forward voltage drop ( V F ) of a power diode is an important electrical parameter for a power diode. Diode with excessive V F can be due to either defects in wafer fabrication or soldering processes. To identify if the defects in soldering process is the root cause to excessive V F , the obvious method will be the method to extract the series resistance from the diode. However, the present series resistance extraction methods are either inaccurate or requires extensive computation time, and they are not practical for failure analysis and process monitoring. In this work, a modified series resistance extraction method is developed. Experimental results showed that the modified method is accurate, and the computation time is short.

Temperature and stress distribution in the SOI structure during fabrication

Silicon wafer bonding technology is becoming one of the key technologies in silicon-on-insulator (SOI) structure fabrication. However, the high-temperature heat treatment during SOI fabrication is inevitable, and the thermal stress thus induced could have an adverse effect on the device fabricated and the bonding interface. In this work, a finite-element analysis software, ANSYS, is used to study the induced mechanical stresses at the interface during the withdrawal of wafers from a high-temperature furnace. It is found that the type of insulators and the geometric dimension of the devices such as the thickness of the work layer, insulator layer, and the substrate thickness are insignificant contributors to the induced thermal stresses. Although it is expected that the furnace temperature and withdrawal velocity are the key factors in determining the mechanical stresses, for the present bonding strength of wafers via wafer bonding technology, the withdrawal velocity must be less than 100 mm/min, and under such a withdrawal velocity, the furnace temperature is also an insignificant factor with regard to the induced stress.

Applications of finite element methods for reliability study of ULSI interconnections

Abstract Three main failure mechanisms of ULSI interconnects are the electromigration (EM), stress induced voiding (SIV) and low- k dielectric breakdown. Reliability tests for these mechanisms are too long to meet the development time requirement, and the underlying dominant mechanisms cannot be identified, rendering difficulty in design-in reliability for integrated circuit. Facing the challenges in the reliability study of the interconnect system, physics based simulation and modeling is found to be essential, and finite element method (FEM) is a suitable tool. A few examples on the application of FEM to study the degradation processes and identification of potential failure sites in interconnects due to EM and SIV are given here. The study of the process induced degradation of the effective k value of low- k dielectric in ULSI interconnect system using FEM is also presented.

Failure mechanisms of aluminum bondpad peeling during thermosonic bonding

Aluminum bondpad peeling was observed in a newly developed thermosonic wirebonding process for chip-on-board assembly. Through detailed failure analysis and with the help of finite element analysis on stress simulation, the true root cause of the peeling is identified. It is found that the true root cause is the effect of skidding force as a result of the constrained movement of the bonding tool as bonding is done on a chip assembled in a plastic casing. With a change in the bonding tool movement, the peeling phenomenon is completely eliminated.

Finite element modeling of residual mechanical stress in partial SOI structure due to wafer bonding processing

The residual mechanical stresses in partial SOI structures generated during wafer bonding processing were simulated using finite element method in this work. By employing the Box-Behnken design for the response surface method, statistical models were established to relate the computational stresses to the structural geometric parameters, including oxide length (and width), oxide thickness and work layer thickness. With these statistical models, the geometrical parameters of the structure could be optimized to effectively reduce the residual mechanical stresses in partial SOI structures.

Modeling of smoothening effect on morphologies of annealed submicron nickel particles used for electrically conductive adhesives

Microelectronic packaging has been accelerating towards adoption of solutions that offer lower cost, higher electrical performance, and better reliability. Flip chip technology lends itself excellently to these goals. The development of anisotropic and isotropic conductive adhesives (ACA and ICA, respectively) as an alternative to solder bumps has received extensive attention in flip chip packaging as it offers an array of advantages such as finer pitch interconnects, green processes, low cost, and low temperature processing. Nickel, with its lower cost than that of silver and better thermal stability than that of copper, appears to be a viable candidate material for ICA and ACA applications. In the present study, a spiky surface morphology of nickel particles synthesized by means of a hydrothermal reduction method was clearly observed. The spiky morphology may have a detrimental effect on the conductivity of the ICA and ACA flip chip interconnect due to its smaller contact surface and propensity towards ...

Development of Physics-Based Modeling for ULSI Interconnections Failure Mechanisms: Electromigration and Stress-Induced Voiding

In this chapter, we present a comprehensive review on the physics-based modeling of EM phenomena in ULSI interconnections over the last three decades. In the evolution of the physics-based modeling, some aspects of the physics are dropped for simplification, and some are added to accommodate new understanding on the EM physics as well as for the new development of the interconnect technology. With the continuous change in the metallization system and materials, the aspects of physics that have been dropped may become important again, and new physics might also occur with these changes in metallization system. Here, we re-examine the justification of dropping or adding various physical aspects in the EM modeling during their evolution and their implications on the future interconnect system.