Yuen-Hui Chee

A 400 /spl mu/W-RX, 1.6mW-TX super-regenerative transceiver for wireless sensor networks

A fully integrated 2GHz super-regenerative transceiver is implemented in a 0.13 /spl mu/m CMOS process. The transmit and receive paths utilize BAW resonators, yielding a 450 /spl mu/W 1V RF front-end and a transmitter delivering 380 /spl mu/W with 23% efficiency. At 5kb/s, the receiver achieves a sensitivity of -100.5dBm for 10/sup -3/ BER.

An ultra-low power MEMS-based two-channel transceiver for wireless sensor networks

This paper explores the design and implementation of a low-power two-channel transceiver using micromachined resonators. Wireless sensor networks require transceivers that are small, cheap, and power efficient. RF-MEMS resonators are utilized to accommodate these constraints. The prototype 1.9GHz transceiver, designed in 0.13 /spl mu/m CMOS, operates at 1.2V and consumes 3mA in receive mode and transmits 1.6dBm with 17% efficiency. The two 40kb/s channels achieve a sensitivity of -78dBm with a 10 /spl mu/s receiver start-up time.

A class A/B low power amplifier for wireless sensor networks

In a dense ad-hoc wireless sensor network, the transmit power is comparable to the circuit power. Linear power amplifiers, which require lower drive power as compared to their switching counterparts, now become viable candidates. This paper presents a class A/B low power amplifier suitable for an ad-hoc wireless sensor network. The amplifier is implemented in a 0.13 /spl mu/m CMOS process and operates with a nominal 1.2 V supply. A capacitive transformer is used to match the antenna to the power amplifier for maximum efficiency. The amplifier achieves 35% drain efficiency while delivering 2.6 mW at 1.92 GHz. With 1.5 V supply, the power amplifier delivers 4.8 mW with 38% drain efficiency.

A Power-Managed Protocol Processor for Wireless Sensor Networks

Wireless sensor network applications, such as environmental control in smart building and ecological monitoring, require low-power nodes that operate their entire lifetime without changing batteries. This paper describes the power management architecture for a digital protocol processor for a sensor network node. Eight subsystems implement the baseband through application protocol layers and are controlled by a centralized power manager. The prototype chip, implemented in 130nm CMOS, operates at 1.0V with an average power consumption of 150muW during normal operation

Ultra-low-power design

In this article, we describe how such an integrated approach has indeed made it possible to produce a PicoNode that meets the original goals. The resulting node combines innovative technologies, such as radio-frequency microelectromechanical systems (RF-MEMS) with ultra-low-power RF and digital integrated circuit (IC) design, and employs aggressive energy-scavenging and packaging techniques. For these technological advances to come to their full fruition, they must be complemented by novel opportunistic networking and wireless protocol schemes that virtually eliminate standby power while still providing robustness

PicoCube: a 1 cm 3 sensor node powered by harvested energy

The PicoCube is a 1 cm3 sensor node using harvested energy as its source of power. Operating at an average of only 6 uW for a tire-pressure application, the PicoCube represents a modular and integrated approach to the design of nodes for wireless sensor networks. It combines advanced ultra-low power circuit techniques with system-level power management. A simple packaging approach allows the modules comprising the node to fit into 1 cm3 in a reliable fashion.

A 46% Efficient 0.8dBm Transmitter for Wireless Sensor Networks

This paper presents a 1.9GHz low power transmitter for wireless sensor networks. It uses film bulk acoustic resonators (FBAR) for RF carrier generation and is co-designed with the antenna. The two-channel transmitter is 46% efficient when radiating 1.2mW from a 650mV supply. With 50% on-off keying, it consumes 1.35mW and supports data rate up till 330kbps. The 1.2times0.8mm2 transmitter is implemented in 0.13mum CMOS and is integrated into a 38times25times8.5mm3 solar powered sensor node

Circuits and Technologies for Wireless Sensor Networks

Successful deployment of wireless sensor and actuator networks in sufficient numbers to provide true ambient intelligence requires the confluence of several disciplines including networking, low power RF and digital IC design, MEMS techniques, energy scavenging, and packaging. Progress in each of these areas has been documented and proof- of-concept prototypes have been tested. Research in RF transceiver design utilizing bulk acoustic wave resonators has yielded fully integrated, ultralow power transceivers. Novel digital circuit design techniques, including aggressive power management, robust subthres- hold logic operation, and ultralow voltage SRAM with data retention enable efficient computation. These technological advances should be accompanied by novel opportunistic networking and media access techniques to provide robustness and decrease the duty cycle of the node. Future challenges include the integration of a sub-50 mW carrier sense detector for asynchronous and non-beaconed receiver wake-up, efficient hybrid energy scavenging power generation, and cheap, robust three-dimensional packaging techniques.

Short Distance Wireless, Dense Networks, and Their Opportunities

Summary form only given. The availability of wireless transceivers transmitting over ranges from few microns to less than half a meter opens the door for a wide range of exciting new applications, ranging from seamless system assembly, smart surfaces, healthcare monitoring and intelligent machinery and components. However, the implementation challenges in terms of size and power for most of these applications are pushing the limits. Fortunately, by exploring the wide range of options offered to the designer, extremely small and virtually zero-power transceivers are feasible. This paper discusses the opportunities, challenges and options of short distance wireless, and illustrates the proposed techniques with several design examples. In addition, the challenges that emerge when trying to embed these nodes into very dense networks are explored. Special consideration is given to the issues of distributed synchronization, localization and robust communication.