Yuichi Nakao

Digital phase locked loop circuit

Low power consuming digital circuit device

Booth array multiplying circuit having carry correction

Data processor including selection mechanism for coupling internal and external request signals to interrupt and DMA controllers

Wait control device

Bus controller for adjusting port size communication between a bus master and bus slave using bus master information

Bus controller for adjusting a bus master to a bus slave

Refresh control circuit

Microcomputer for accessing a memory outside the chip by using an address generated from the CPU

Digital circuit device