Yuichiro Murachi

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

SUMMARY This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ringconnected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45–73% in comparison to cases with conventional

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

This paper describes a 95mW MPEG2 MP@HL motion estimation processor core for portable and high resolution video application like an HD camcorder. It features a novel hierarchical algorithm and a low power ring-connected systolic array architecture. It supports the frame/field and bi-directional prediction with half-pel precision for 1920/spl times/1080@30fps resolution video. The search range is /spl plusmn/128/spl times//spl plusmn/64. The ME core integrates 2.25M transistors in 3.1mm/spl times/3.1mm using 0.18micron technology.

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition

SUMMARY This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lu- cas and Kanade (PLK) algorithm. It features a smaller chip area, higher pixel rate, and higher accuracy than conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original PLK algorithm improve the optical-flow accuracy, and reduce the proces- sor hardware cost. Furthermore, window interleaving and window overlap methods reduces the necessary clock frequency of the processor by 70%, allowing low-power characteristics. We first verified the PLK algorithm and architecture with a proto-typed FPGA implementation. Then, we de- signed a VLSI processor that can handle a VGA 30-fps image sequence at a clock frequency of 332 MHz. The core size and power consumption are estimated at 3.50 × 3.00 mm 2 and 600 mW, respectively, in a 90-nm process

A 95mW MPEG2 MP@HL motion estimation processor core for portable high resolution video application

This paper describes a 95mW MPEG2 MP@HL motion estimation processor core for portable and high resolution video application like an HD camcorder. It features a novel hierarchical algorithm and a low power ring-connected systolic array architecture. It supports the frame/field and bi-directional prediction with half-pel precision for 1920/spl times/1080@30fps resolution video. The search range is /spl plusmn/128/spl times//spl plusmn/64. The ME core integrates 2.25M transistors in 3.1mm/spl times/3.1mm using 0.18micron technology.

A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing

This paper describes a unique SRAM architecture for super- parallel video processing. It features one cycle functional access of a rectangular image data (n x m pixels) with segmentation-free. To achieve this accessibility, a local word-line select scheme and a merged X-decoder method are newly introduced with elimination of extra X-decoder employed in usage of the conventional divided SRAM macro. The proposed SRAM has been adopted to a search window buffer for H.264 motion estimation processor for HDTV resolution video. As a result, a power and area of the search window buffer are reduced by 49% and by 48%, respectively. Furthermore, it is shown that the proposed SRAM is more efficient for super-HDTV resolution video which requires more parallelism.

A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer

We describe a sub 100-mW H.264 MP@L4.1 integerpel motion estimation processor core for low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bidirectional prediction for a resolution of 1920×1080 pixels at 30fps. The proposed processor features a novel hierarchical algorithm, reconfigurable ring-connected systolic array architecture and segmentation-free, rectangle-access search window buffer. The hierarchical algorithm consists of a fine search and a coarse search. A complementary recursive cross search is newly introduced in the coarse search. The fine search is adaptively carried out, based on an image analysis result obtained by the coarse search. The proposed systolic array architecture minimizes the amount of transferred data, and lowers computation cycles for the coarse and fine searches. In addition, we propose a novel search window buffer SRAM that has instantaneous accessibility to a rectangular area with arbitrary location. The processor core has been designed with a 90nm CMOS design rule. Core size is 2.5×2.5mm2. One core supports one-reference-frame and dissipates 48mW at 1V. Two core configuration consumes 96mW for two-reference-frame search.

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing

For super-parallel video processing, we proposed a power-and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in word-lines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces a power and area by 57-60% and 60%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (2-read port SRAM with eight-parallel architecture) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 μW for QCIF 15-fps in a 130-nm technology.

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing

For super-parallel video processing, we proposed a power- and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces an area and power by 69% and 59%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (eight-division and 2-read port SRAM) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 muW for QCIF 15-fps in a 130-nm technology

An 800-μW H.264 Baseline-Profile Motion Estimation Processor Core

This paper describes an 800-μW H.264 baseline- profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy, a reconfigurable SIMD/systolic-array datapath architecture and a power-efficient novel SRAM circuit with a segmentation-free and horizontal/vertical accessibility. The proposed architecture can reconfigure datapath to either an SIMD or systolic array depending on processing flow. The segmentation-free access means concurrent accessibility to arbitrary consecutive pixels. The processor supports all the seven kinds of block modes, and can handle three reference frames for a VGA (640 × 480) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8 × 3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW for QCIF 15-fps with one reference picture.

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding

This paper describes an H.264/AVC MP@L4.1 quarter-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 times 1080 pixels at 30 fps which havenpsilat been realized by conventional methods yet. The proposed processor consists of four modules for low power consumption: a module for an integer-pel motion estimation, a segmentation-free rectangle-access search window buffer, a module for quarter-pel motion estimation, and a module reducing candidate motion vectors. We propose an adaptive algorithm that reduces a workload and power in quarter-pel motion estimation. The algorithm and architecture for the candidate motion vectors reduction suppress a workload of the following process. The processor core has been designed in a 90 nm CMOS technology. The core size is 6.0 times 6.0 mm2. With this core, two reference frame can be handled, and 160.1 mW is consumed at 1.0 V.