Masayuki Miyama

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution

Four definitions of static random access memory (SRAM) cell write margins (WMs) were reexamined by analyzing the dependence of the WM on the SRAM cell transistor threshold voltages (Vths) in order to find a preferable definition. The WM is expected to obey the normal distribution if the differential coefficients of the WM to Vths are constant over a wide range of Vth variations. This means that the write yield can be easily predicted by a small number of measured samples. Using SPICE in 45-nm technology, we examined which definition had Vth linearity, as well as giving an accurate write limit. The distribution predicted from the linearity was verified by the Monte Carlo simulation. As a result, the definition proposed by Gierczynski was found to be the most suitable definition for predicting the distribution and the write yield.

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit

An adiabatic 64-kb SRAM circuit with shared reading and writing ports was designed, which enables gradual charging and discharging while maintaining a large VDD so that the problems of VT variation and electromigration in the nanocircuit can be solved. In the writing mode, the voltage of the memory cell ground line is increased to VDD/2 gradually, and the nMOSFET is turned off so that the memory cell ground line is set in a high-impedance state. Data can then be written easily by decreasing the voltage of one bit line adiabatically, while the voltage of the other bit line remains high. For reading, using the shared reading port, the voltage swing of the global bit-line can be decreased to VDD/4 so that the problems of electromigration can be solved. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and confirmed that the number of transistors in the cell is quasi-six. In addition, two types of new step voltage circuits with tank capacitors are proposed. One is for producing the memory cell ground line voltage and the other for charging the word line voltage adiabatically. Spontaneous step voltage formation is confirmed experimentally.

A Wireless-Interface SoC Powered by Energy Harvesting for Short-range Data Communication

This paper describes the design and estimation of a wireless-interface SoC for wireless battery-less mouse with short-range data communication capability. It comprises an RF transmitter and microcontroller. An SoC, which is powered by an electric generator that exploits gyration energy by dragging the mouse, was fabricated using the TSMC 0.18-mum CMOS process. Features of the SoC are the adoption of a simple FSK modulation scheme, a single-end configuration on the RF transmitter, and the specific microcontroller design for mouse operation. We verified that the RF transmitter can perform data communication with a 1-m range at 2.17 mW, and the microcontroller consumes 0.03 mW at 1 MHz, which shows that the total power consumption in the SoC is 2.2 mW. This is sufficiently low for the SoC to operate with energy harvesting

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

SUMMARY This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ringconnected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45–73% in comparison to cases with conventional

A sub-mW MPEG-4 motion estimation processor core for mobile video application

This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a Gradient Descent Search algorithm whose computation power is only 7% of the conventional 1:4-subsampling search, producing higher picture quality. Another feature is an optimized SIMD datapath architecture to decrease a clock frequency and an operating voltage. It has been fabricated with CMOS 5-metal 0.18 um technology. The measured power consumption to process a QCIF 15 fps video is 0.4 mW under 0.85 MHz@1.0 V.

Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage

An adiabatic 1-kb SRAM circuit was designed, which enables gradual charging during writing and reading while maintaining a large VDD so that the problems of VT variation and electromigration in the nanocircuit can be resolved. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that the memory cell power line is set in a high-impedance state. Then, we can write data easily by inputting adiabatic signal from one bit line, while the other bit line is set to ground. For reading, a verifying operation is proposed for resolving the electromigration problem. The word line voltage is changed stepwise while the voltages of the bit lines are verified. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and found that there is no area penalty. In addition, a new charge recycle circuit with tank capacitors is proposed.

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

This paper describes a 95mW MPEG2 MP@HL motion estimation processor core for portable and high resolution video application like an HD camcorder. It features a novel hierarchical algorithm and a low power ring-connected systolic array architecture. It supports the frame/field and bi-directional prediction with half-pel precision for 1920/spl times/1080@30fps resolution video. The search range is /spl plusmn/128/spl times//spl plusmn/64. The ME core integrates 2.25M transistors in 3.1mm/spl times/3.1mm using 0.18micron technology.

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage

A single-bit-line (BL) static RAM (SRAM) circuit that employs adiabatic charging of a word line during a read operation was found to provide a large dynamic noise margin (DNM) for reading. Single-BL reading is achieved by using a left access transistor and a shared reading port. The shared reading port greatly reduces the BL capacitance, enabling the voltage of the BL connected to the low-voltage node of the flip-flop to change from the precharge voltage to GND. An analysis of the time-wise change in DNM revealed that the read noise margin of this circuit was 1.9 times larger than that of a conventional two-BL circuit. This circuit enables the design of an SRAM that is smaller than a conventional one, resulting in lower energy consumption.

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation

An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.02 x 5.33 mm 2 with six-metal 90-nm CMOS technology.

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition

SUMMARY This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lu- cas and Kanade (PLK) algorithm. It features a smaller chip area, higher pixel rate, and higher accuracy than conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original PLK algorithm improve the optical-flow accuracy, and reduce the proces- sor hardware cost. Furthermore, window interleaving and window overlap methods reduces the necessary clock frequency of the processor by 70%, allowing low-power characteristics. We first verified the PLK algorithm and architecture with a proto-typed FPGA implementation. Then, we de- signed a VLSI processor that can handle a VGA 30-fps image sequence at a clock frequency of 332 MHz. The core size and power consumption are estimated at 3.50 × 3.00 mm 2 and 600 mW, respectively, in a 90-nm process