Yukihiro Kumagai

Effect of external stress on polarization in ferroelectric thin films

The polarization changes caused by applying mechanical stresses to a lead zirconate titanate (PZT) thin film were investigated. Both the remnant and spontaneous polarizations decreased when the PZT film was loaded with tensile stress. For compressive stresses, the remnant polarization increased, but spontaneous polarization did not change. In fatigue with tensile stress state, the polarization decreased earlier than when there was no stress, which depend on whether or not the initial polarization value was high. Conversely, in fatigue with compressive stress, the initial higher remnant polarization value was maintained compared with the polarization in the unstress condition.

Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics

Active-area layout dependence of MOSFET parametric characteristics and its reduction by reducing shallow trench isolation (STI)-induced mechanical stress were investigated. Threshold voltages (V/sub th/) and saturation drain currents (I/sub ds/) become sensitive to the active-area layout of MOSFET in scaled-down technology. This phenomenon is the effect of mechanical stress from STI edge, which reduces impurity diffusion in channel region and enhances carrier mobility. To reduce the STI-induced stress, we examined STI-wall-oxide nitridation and STI gap-fill-oxide densifying in pure N/sub 2/ ambient. These processes reduced the reoxidation of the STI wall oxide, therefore reduced the STI-induced stress. According to the new STI process, the active-area layout dependence of V/sub th/ and I/sub ds/ were reduced successfully.

Thermal Stability of Pt Bottom Electrodes for Ferroelectric Capacitors

The stress of Pt films deposited at various temperatures and its correlation with the formation of hillocks during heat treatment were investigated. The residual stress changes from compressive to tensile as the deposition temperature increases. The compressive residual stress of a Pt film deposited at room temperature is initially relaxed by the shrinkage of the film thickness and then by hillock formation at a certain maximum compressive stress when the Pt film is heat-treated. On the other hand, Pt films deposited at higher temperatures (up to 500°C) have a high tensile residual stress. The Pt film maintains its smooth surface and no hillocks appear during the heat treatment at 500°C when the residual stress is tensile, since the threshold temperature at which hillocks form increases.

Stress Analysis for Chip–Package Interaction of Cu/Low-

Delamination failure of a low-k interlayer dielectric (ILD) layer of Cu/low-k multilayer interconnects during a thermal cycle test was investigated by mechanical stress simulation. A three-dimensional (3D) multilevel modeling method was used to analyze the stress that occurred in a fine-scale film stack in a large-scale package. The maximum stress occurred at the low-k/cap film interface that was located at the bottom surface of the low-k ILD layer. This maximum-stress interface coincides with the interface where the delamination occurred. Using this method, the effects of the number of ILD layers, the Youngs modulus of the ILD, and the package type on the failure were investigated. This method is useful for reducing delamination failure.

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We have developed a new 12 V LDMOS transistor for 0.25 μm power ICs, which is designed from the viewpoint of mechanical stress to reduce on-resistance. A critically low resistance substrate has been developed to reduce the resistance from the surface source to the backside of the transistor, avoiding compressive stress due to high boron doping in the substrate. A buried-polysilicon sinker is utilized to apply tensile stress to the channel and the offset-drain region. The existing mechanical stress distribution is confirmed by two-dimensional UV-Raman spectroscopy. The transconductance of the LDMOS transistor is increased by 12% owing to the tensile stress and the total on-resistance is reduced by 16% owing to the channel and source resistance reduction, which directly leads to a higher efficiency of analog power circuits.

Multilayer Interconnects

We have developed a new laterally diffused metal–oxide–semiconductor (LDMOS) transistor, which is designed from the viewpoint of mechanical stress to reduce on-state resistance. A critically low resistance substrate has been developed to reduce the resistance from the surface source to the backside of the transistor, avoiding compressive stress due to high boron doping in the substrate. A buried-polysilicon sinker is utilized to apply tensile stress to the channel and the offset-drain region. The polysilicon sinker is deposited as amorphous silicon and crystallized through a thermal process after deposition. The existing mechanical stress distribution is confirmed by two-dimensional UV-Raman spectroscopy. The transconductance of the LDMOS transistor is increased by 12% owing to the tensile stress and the total on-state resistance is reduced by 16% owing to the channel and source resistance reduction, which directly leads to a higher efficiency of analog power circuits.

Low-on-resistance strain-controlled LDMOS transistors for 0.25-μm power ICs

1. fntroduction With the trend towards high integration of LSIs, the mechanical stress in a device has been increasing rapidly because of the high intrinsic stress in thin films. The stress developed in recent MOSFETs sometimes exceeds a few hundred mega pascals, which is high enough to cause a change in the transistor characteristics. That is, the mechanical stress can change the drain current of an 100-nm MOSFET more than llVo [1, 27. The change occurs as a result of the piezoresistance effect caused by residual stress in a silicon substrate [3]. It is thus very important to control the mechanical stress in 100-nm MOSFET devices in order to improve mechanical reliability and electronic performance. In this work, we clarified the strain (stress) sensitivity of drain current of a 0.l3-pm-node MOSFET, and developed a method for predicting the change in MOSFET drain current caused by thin-film processing.

Strain-Controlled Laterally Diffused Metal–Oxide–Semiconductor Transistor Utilizing Buried-Polysilicon Sinker as Stressor

The hillock growth mechanism at the surface of Pt/TiN electrodes is investigated. TEM and SEM observations confirm that local delamination occurs at the Pt/TiN interface first, and then, plastic deformation of the Pt films under compressive stress forms hollow domes, which result in hillocks. Hillocks always start to grow when the internal stress in the Pt films reaches about −1000 MPa during annealing in N 2 /O 2 ambient. Since the initial internal stress of Pt thin films varies from −500 to 500 MPa, depending on their deposition temperature, the hillock growth temperature strongly depends on the deposition temperature of the Pt films. It is very important, therefore, to control the initial internal stress in Pt films in order to eliminate hillock growth at the surface of Pt/TiN electrodes.