Masafumi Miyamoto

Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics

Active-area layout dependence of MOSFET parametric characteristics and its reduction by reducing shallow trench isolation (STI)-induced mechanical stress were investigated. Threshold voltages (V/sub th/) and saturation drain currents (I/sub ds/) become sensitive to the active-area layout of MOSFET in scaled-down technology. This phenomenon is the effect of mechanical stress from STI edge, which reduces impurity diffusion in channel region and enhances carrier mobility. To reduce the STI-induced stress, we examined STI-wall-oxide nitridation and STI gap-fill-oxide densifying in pure N/sub 2/ ambient. These processes reduced the reoxidation of the STI wall oxide, therefore reduced the STI-induced stress. According to the new STI process, the active-area layout dependence of V/sub th/ and I/sub ds/ were reduced successfully.

A high-current-gain low-temperature pseudo-HBT utilizing a sidewall base-contact structure (SICOS)

A silicon pseudo-heterojunction bipolar transistor (HBT) with a current gain of over 100 at 77 K has been successfully fabricated using the upward operation of a self-aligned sidewall base-contact structure (SICOS). The measured characteristics agree well with the theoretical prediction, showing a negative exponential temperature dependence of current gain and a 2500-times larger collector current than in the conventional transistor at 77 K. This makes homojunction bipolar transistor operation at low temperatures feasible and has the potential to overcome the bipolar/BiCMOS limitations.<<ETX>>

Strained-silicon MOSFETs for analog applications: utilizing a supercritical-thickness strained Layer for low leakage current and high breakdown Voltage

Strained-silicon MOSFETs with both high breakdown voltage and low leakage current needed for RF/analog applications were investigated. Proper control of junction-depth profile and strained-silicon-layer thickness significantly improved transconductance, on resistance, and leakage current. Breakdown voltage of strained-silicon MOSFETs was the same as silicon MOSFETs even at elevated temperatures. RF/analog performances, such as cutoff frequency and 1/f noise, were improved by this technology while keeping high-driving-voltage capability.

Pass transistor based gate array architecture

This paper describes a completely new gate array architecture that fully exploits inherent advantages of pass transistor logic which a conventional architecture can not. In implementing SRAMs, our gate array achieves a 1.5 times higher density than a conventional gate array due to its different size transistors in the basic cell. An 8/spl times/8 b multiplier designed with this gate array using 0.4-/spl mu/m CMOS process achieves a multiplication time of 12.7 ns and dissipates 480 /spl mu/W with the supply voltage of 1.2 V. A 1.2 V 9 ns 1 kb SRAM was also designed with the same gate array.

High performance RF power LDMOSFETs for cellular handsets formed in thick-strained-Si/relaxed-SiGe structure

We applied a strained-Si/relaxed-SiGe structure to LDMOSFETs in order to improve the power-added efficiency (PAE) of cellular handset RF power amplifier applications. Our LDMOSFETs were fabricated in a 70-nm-thick strained-Si/relaxed Si0.85Ge0.15 structure. Despite of appearance of misfit dislocations, the thick strained-Si was essential for the high efficiency and low leakage. The self-heating effects on the power performance were estimated to be negligible by using a dynamic thermal simulation. The devices exhibited 46.7%-PAE at 27.5 dBm-Pout for WCDMA a handset application, which was improved by 4.0 point over Si controls

A high-current-gain low-temperature pseudo-heterojunction bipolar transistor utilizing sidewall base-contact structure (SICOS)

An experimental pseudo-heterojunction bipolar transistor (HBT) is described. The pseudo-HBT is a homojunction bipolar transistor having a moderately doped emitter and a heavily doped base, providing a bandgap profile similar to those of actual HBTs. Analyses including real constraints, such as a heavily doped emitter region for ohmic contact and the profile tail in the base region, show a significant change in the way they affect injection characteristics between 300 and 77 K. Based on these analyses, an impurity profile is carefully designed for upward mode operation. The electron injection into the external base region. which is thought to be unfavorable for high current gain in the upward mode, is avoided by using the sidewall base-contact structure. The fabricated transistor clearly displays a negative temperature dependence on current gain. The current gain is 107 at 77 K, which is 5 times higher than the room-temperature current gain. In addition, current gain excluding the nonideal effects at 77 K is as high as 25,000. These results not only remove gain degradation at low temperatures, but also verify the pseudo-HBT concept, in which an injection efficiency as high as that of an HBT can be obtained using only homojunctions. Based on these results, the small emitter transit time inherent in pseudo-HBTs is analyzed. >

0.3-/spl mu/m mixed analog/digital CMOS technology for low-voltage operation

A 0.3-/spl mu/m mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si/sub 3/N/sub 4/ capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm. >

1.2 V mixed analog/digital circuits using 0.3 /spl mu/m CMOS LSI technology

Although dropping the supply voltage below 2 V is effective in reducing power consumption of LSIs for low-power systems, it has not been adopted because it severely degrades the system performance. This paper reports an experimental 1.2 V mixed analog/digital LSI based on 0.3 /spl mu/m laterally-doped buried-layer (LDB) CMOS with /spl plusmn/0.4 V threshold voltages. Based on circuits such as a double feedforward phase-compensated amplifier and a self current cut-off sense amplifier, a 9b 2 MHz 4 mW pipelined A/D converter, a 16 kb 2 mW SRAM with 32 ns access time, and a basic logic gate with a 400 ps delay and 0.4 /spl mu/W/MHz dissipation are realized.<<ETX>>

Thick-Strained-Si/Relaxed-SiGe Structure of High-Performance RF Power LDMOSFETs for Cellular Handsets

A strained-Si/relaxed-SiGe structure was applied to laterally diffused MOSFETs (LDMOSFETs) in order to improve the PAE of cellular handset RF power-amplifier applications. The LDMOSFETs were fabricated in a 70-nm-thick strained-Si/relaxed-Si0.85Ge0.15 structure. Despite the appearance of misfit dislocations, the thick strained-Si was essential for high efficiency and low leakage. The self-heating effects on the power performance were estimated to be negligible by using dynamic thermal simulation. The devices exhibited 46.6% PAE at a Pout of 27.5 dBm for wideband code-division multiple-access handset applications, which was a 3.8-point improvement over Si controls

Strained-silicon MOSFETs of low leakage current and high breakdown voltage for analog applications

Strained-silicon MOSFETs of both high breakdown voltage and low leakage current were fabricated by employing a thick strained-silicon layer. It is demonstrated that proper control of junction depth can drastically reduce leakage current although misfit dislocations exist at the strained-silicon/SiGe interface, and that breakdown voltage of strained-silicon MOSFETs kept the same high value as silicon MOSFETs even at elevated temperatures. RF performances such as f/sub T/, noise, and FR-power-amplifier efficiency were improved by this technology.