Yukito Tsunoda

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies.

8.9 A 40Gb/s VCSEL over-driving IC with group-delay-tunable pre-emphasis for optical interconnection

High-speed and high-density interconnections between racks and modules in the high-performance computing systems and data centers are currently being developed. The transmission range of conventional electrical interconnections is limited due to the bandwidth of electrical channels. VCSEL-based optical interconnection technologies are a promising solution for overcoming bandwidth bottlenecks in large scale computing systems [1-3]. Although it is anticipated that the next challenge for optical interconnections is to move to a serial data-rate of 40Gb/s, there are few 40Gb/s class VCSELs at present. Overdriving is a method that boosts high-frequency response to overcome the VCSEL speed limit [4,5]. To develop high-density optical interconnections, a low-power over-driving IC is a key technology. In addition, the optical modulation amplitude (OMA) must be increased to enable long-distance transmission in large scale computing systems as a data center. To achieve this large modulation amplitude, we must overcome the jitter issue caused by the intrinsic group delay of VCSELs. In this paper, we present a 40Gb/s driver IC for over-driving a 25Gb/s VCSEL using a new 2-tap pre-emphasis circuit with tunable group-delay compensation. This circuit compensates for the complex group delay of VCSELs. With this circuit, we achieve 40Gb/s low-jitter operation with 2.3dBm OMA and reduce the power consumption to as low as 312mW/ch.

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

Compact photonic gateway for dynamic path control using acousto-optic tunable filter

A compact photonic gateway for wavelength-path control with a simple configuration at low cost was developed. The gateway achieves wavelength-path control by using acousto-optic tunable filters (AOTF). The fabricated four-channel integrated AOTF device exhibits a high performance with regard to polarization-independent characteristics, side-lobe suppression, higher extinction ratio, and narrower bandwidth for 100 GHz spacing. An AOTF subsystem was fabricated by combining an AOTF with the control circuit to exploit the AOTFs high-speed switching to the full and operate it stably for practical use and achieve stable operation of the AOTF. We manufactured the photonic gateway node by assembling the AOTF subsystem with the provisioning control and redundant system.

25-Gb/s transmission over 250-m MMF using over-drive of 10-Gb/s VCSEL by utilizing asymmetric pre-emphasis

We developed a 25-Gb/s transmitter with an over-drive of 10-Gb/s VCSEL using our asymmetric pre-emphasis design. Owing to the narrow spectral width characteristics of our transmitter, we demonstrate 25-Gb/s transmission over 250-m of multimode fiber.

High-Bandwidth Optical Interconnect Technologies for Next-Generation Server Systems

We present optical interconnect technologies to realize next-generation server systems. We propose blade server architecture with optical bus-extensions for expanding consolidation, and demonstrate our cost-effective optical transceiver technologies for high-bandwidth interconnects.

Cost-effective transceiver technologies for high-bandwidth optical interconnection in high-end server systems

We have developed cost-effective technologies for optical transceivers with over 10-Gb/s operations in high bandwidth interconnection. These include optical engines on flexible printed circuit and 25Gb/s operation with pre-emphasis overdrive of conventional VCSEL for 10Gb/s.

Twenty-five gigabit per second transmitter using pre-emphasis

High-performance computing (HPC) systems and high-end blade servers are currently being developed for larger scale, more complex simulations in the fields of life and earth sciences. Naturally, these systems also require high-speed, highdensity interconnections between racks, modules, and chips. However, conventional electrical interconnection technologies are approaching their critical limit owing to the limited bandwidth of electrical channels. The wide bandwidth of optical signals, on the other hand, makes optical interconnections a promising solution to this restriction. To introduce optical interconnections in computing systems, the optical interface not only must be high speed but also small and affordable. Direct modulation using vertical-cavity surface-emitting lasers (VCSELs) is a suitable means of assuring these properties. In fact, 10Gb/s optical interconnections using VCSELs have already been reported and are starting to appear in some HPC systems.1 According to Ethernet and InfiniBand standards, the market demand for bandwidth has been increasing steadily and soon will reach 25Gb/s/lane. Although VCSELs operating at this rate have been explored as transmitter elements for optical interconnections,2, 3 using commercial 10Gb/s standard VCSELs for a 25Gb/s transmitter is actually an effective way of reducing costs. Here, we describe just such a configuration using pre-emphasis technology.4 The intrinsic optical dynamics of 10Gb/s VCSELs are slow, which in turn degrades the data signal. For this reason, we applied a pre-emphasis pulse-shaping technology to achieve 25Gb/s. Figure 1 shows a schematic of our VCSEL transmitter. By enhancing the high-speed signal in advance, the device driver compensates for the laser’s lack of speed and improves the output waveform. Figure 1. Vertical-cavity surface-emitting laser (VCSEL) transmitter using a pre-emphasis driver. The enhanced signal compensates the suboptimal VCSELs and improves the output waveform.

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS

To meet increasing demands for server computational power, high-density, multilane links with a data rate exceeding 25Gb/s/lane are needed. An optical transceiver with a retiming capability would significantly enhance the usability of the link by extending the reach. Such optical transceivers should operate without an external clock source since a small form factor is imperative. The optical link we develop has a four-lane configuration that consists of an electrical-to-optical (E/O) converter and an optical-to-electrical (O/E) convertor (Fig. 22.7.1). Both the E/O and O/E convertors are equipped with a per-lane reference-less clock-and-data recovery (CDR) circuit that enables independent operation of each lane. The transceiver pitch is 250μm/lane, which matches the fiber pitch of the optical-fiber array used in the link. Since the jitter added by the CDR should be minimized in retimer applications, an LC-VCO is a preferable choice for clock-signal generation. At this transceiver pitch, however, the coupling through mutual inductances between LC tanks has a significant impact on the CDR characteristics. To address this concern, we analyze the impact of inter-VCO coupling and design the CDR so that the coupling does not affect the CDR performance. Each lane of the E/O convertor consists of a continuous-time linear equalizer (CTLE), a CDR, and a VCSEL driver with a two-tap feed-forward equalizer (FFE) (Fig. 22.7.1). Each lane of the O/E convertor has a trans-impedance amplifier (TIA) stage followed by a limiting amplifier (LA), a CDR, and an electrical-line driver with a two-tap FFE. All the CDRs have an identical design consisting of a flip-flop for the data decision, a selector for bypass-mode operation, a Pottbacker type phase-frequency detector (PFD) [1], a charge pump (CP), a lag-lead filter, and a quadrature LC-VCO (QVCO). During the bypass mode, the CDR loop is set into a power-down mode where the VCO does not oscillate.

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS

The optical interconnect technologies are a promising solution for high-speed and high-density interconnects because of the high-bandwidth and low-crosstalk properties of optical signals. The next challenge for optical interconnects is to move to a serial data-rate of 25Gb/s or higher [1,2]. To achieve flexible interconnects on a bandwidth demand, a CDR is required to operate at multiple rates in a wide tuning range. A selectable multi-VCO structure is one method to overcome this issue. However, when multi-VCOs are allocated in each channel, the large size of VCOs makes it difficult to achieve a high-density optical link. In this paper, we presenta dual-loop hybrid CDR including a phase interpolator (PI) loop for phase tracking and a common VCO loop situated outside the channel areas for frequency acquisition. We develop a quadrant-switching analog Pl-loop that has the ability to track the frequency mismatch corresponding to full-rate frequency up to 35Gb/s. The 4-channel driver IC with this dual-loop hybrid CDR is fabricated in 0.13μm SiGe BiCMOS technology. With these circuits, we achieve a driver IC with a multi-rate, ranging from 24 to 35Gb/s, reference-less CDR for flexible optical interconnects.