Takayuki Shibasaki

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range

Quadrature injection-lockedLC dividers with either a Miller topology or an injection-lockedLC VCO topology are coupled with transconductors to enhance their locking range. The effect of the transconductance coupling is analyzed theoretically and through circuit simulation. Both topologies were fabricated by 90-nm CMOS technology with a target input center frequency of 20 GHz and output frequency of 10 GHz. The measured locking range for the Miller topology with transconductance coupling is 25.3%, compared to 20.9% without coupling. The measured locking range for the injection-locked LC VCO topology with transconductance coupling is 18.1%, compared to 12.9% without coupling. Moreover, power consumption for both dividers is 6.4 mW with a 1.2-V supply.

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies.

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

A 56-Gb/s receiver front-end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front-end operates at 56Gb/s with a bit error rate of less than 10-12 with a 0.4UI margin in the bathtub curve. It occupies 0.27mm2 and consumes 177mW of power from a 0.9-V supply.

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1-3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a complete transceiver.

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current standards. Though transceivers for a data rate over 25Gb/s have been reported [1-3], designing clock-generating circuits for the receiver front-end is a significant challenge. In a phase interpolator (PI) commonly used in conventional receivers for a multi-channel configuration, both the linearity and frequency characteristics of the circuit affect the interpolation accuracy since it dynamically interpolates between reference clock signals supplied from a PLL, making the design more difficult. Blind-clock ADC-based receivers [4] eliminate the need for a clock-phase-adjusting circuit, but the area and power overheads are large due to high-sampling-rate ADCs. To address these issues, we fabricate and test a 28nm CMOS blind-clock receiver that performs phase tracking by using a data interpolator (DI). We confirm error-free operation of the receiver up to 32Gb/s with power consumption of 308.4mW from a 0.9V power supply.

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS

A 60-GHz injection-locked frequency divider (ILFD) fabricated in 65nm CMOS and operating at 1.2V consumes 1.65mW excluding buffers and biasing circuits, and has a measured locking range of 48.5–62.9GHz (25.9%) with 0dBm input power. The core ILFD area is 0.0157mm2. The large locking range is attributed to the use of the multi-order LC oscillator topology.

A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range

A 20-GHz injection-locked LC divider is described. A Miller divider topology was employed along with a coupling circuit to maximize the locking range. A test chip designed in a 90nm CMOS technology operates at 20 GHz with 25% locking range while consuming 6.4 mW of power

18-GHz Clock Distribution Using a Coupled VCO Array

This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process

A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind clock signal, which has a plesiochronous frequency-phase relation with the data. Phase alignment between the data and decision timing is achieved by interpolating the input-signal samples in the analog domain. The receiver has a continuous-time linear equalizer and a two-tap loop unrolled DFE using adjustable-threshold comparators. The receiver occupies 0.24 mm2 and consumes 308.4 mW from a 0.9-V supply when it is implemented with a 28-nm CMOS process.