Hirotaka Tamura

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.

Technique for controlling effective Vth in multi-Gbit DRAM sense amplifier

We propose the use of a capacitor couple structure to control the effective threshold voltage (Vth) and its application to Vth fluctuation compensation in flip-flop sense amplifiers for multi-gigabit DRAMs. Our proposed sense amplifier functions correctly at up to a 500 mV fluctuation in Vth for the transistor pair in the latch. It does not require extra charging time in the sensing operation for compensation. In addition, the sense-amplifier speed is independent of the Vth value, so our S/A can also compensate the sensing speed fluctuation. This Vth control method and Vth-compensated sense amplifier opens up the possibility of utilizing transistors with gate lengths of less than 0.1 /spl mu/m, where the Vth variations could not be reduced.

40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS

A 1.2V 40Gbit/s 4:1 MUX and 1:4 DEMUX are implemented in a in 90nm digital-compatible standard CMOS technology. The MUX and DEMUX operate from a 1.2V supply and draw 110mA and 52mA, respectively. Experimental results show a clear eye opening of 300mV/sub pp/ for the MUX and that of 540mV/sub pp/ for the DEMUX at 40Gbit/s.

Partial response detection technique for driver power reduction in high speed memory-to-processor communications

A partial-response detection technique cuts the driver power by up to 85% in memory-to-processor communication with several hundred MHz data rates. The signaling scheme reduces driver power by reducing the transistor width and raising the termination resistance above the the characteristic impedance. This results in a reduction of the signal bandwidth and thus a large inter-symbol interference (ISI). This side effect is offset by detecting the partial response of the transmitted signal, in which the ISI is subtracted from the signal. The receiver samples the data at half-periods of the clock. It employs a delay-locked loop to time sampling at the end of each symbol period of length T, to fully exploit signal current integrated in the signaling line during that period.

5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking

A 6 ns-latency 12 mW 5 Gb/s bidirectional link for short-haul (<5 m) balanced lines uses an on-chip switched-capacitor hybrid with echo-canceling capability. The clock-recovery circuit, based on a phase interpolator, makes the link tolerant to a 100 ppm difference between the frequencies of the transmit and receive clocks.

A CMOS multi-channel 10Gb/s transceiver

A quad 10Gb/s transceiver in 0.11/spl mu/m CMOS communicates electric signals over balanced copper media. The transceiver uses a single 1.2V power supply and dissipates 415mW per channel. One PLL supplies a reference clock to two transmitter channels and two receiver channels. The transceiver contains analog front ends, clock recovery units, and 312MHz parallel interfaces.

5-6.4 Gbps 12 channel transceiver with pre-emphasis and equalizer

A 5 Gbps to 6.4 Gbps transceiver consists of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO PLLs, and a clock recovery unit. The Tx has a 5-tap pre-emphasis filter, and the Rx has an equalizer with intersymbol interference (ISI) monitor. Monitoring the ISI enables a fine adjustment of the loss compensation. The pre-emphasis filter in the Tx and the equalizer in the Rx can compensate for a transmission loss of up to 20 dB and 15 dB at 6.4 Gbps, respectively. The areas of the Tx and Rx channels including the PLLs are both 3.92 mm/sup 2/. The transmitter dissipates 150 mW/channel at 6.4 Gbps when compensating for a loss of 20 dB, the receiver 90 mW/channel when compensating for 15 dB loss.

A 0.9 V sense-amplifier driver for high-speed Gb-scale DRAMs

We proposed a new sense-amplifier driver for low power, high-speed Gb-scale DRAMs. Our sense amplifier is temporally isolated from the bit line and we use overdriving with boost capacitors, to operate at a Vcc of down to 0.8 V. A charge recycle technique using a new charge-transfer transistor driver is employed to reduce power consumption in the additional controlling circuits. SPICE simulation showed that the access time was 2.7 ns faster than the conventional method, and the power consumption to isolate the bit lines and overdrive the sense amplifier was reduced by 28% using the charge recycle technique.