Yulong Han

Monte Carlo simulation of extraction barrier width effects on terahertz quantum cascade lasers

The effect of extraction barrier width on the performance of a resonant-phonon terahertz quantum cascade laser is studied using the ensemble Monte Carlo method. The width of extraction barrier is varied from 48to33A with a stepsize of −3A. The calculated threshold current density increases monotonously from 436to1054A∕cm2 with decreasing extraction barrier width, while the peak gain shows nontrivial behavior. These findings agree well with an experimental study. The simulation results suggest an optimal extraction barrier width of 36A for peak gain and for the best temperature performance.

Investigation of charge loss mechanism of thickness-scalable trapping layer by variable temperature Kelvin probe force microscopy

In this letter, the retention properties of charge trapping memory with decreased thickness of ultra-thin HfO2 charge trapping layer are investigated by Kelvin probe force microscopy (KFM) technology. Experiment results show that retention properties became worse with the reducing of HfO2 thickness and increasing of temperature. Based on total remaining charge density and lateral leakage charge density extracted from the contact potential differences, we find that vertical charge leakage acted as a dominant role of charge loss with respect to lateral charge redistribution. Furthermore, effective trap energies are extracted from KFM analysis at high temperatures and it is concluded that the suppression of lateral charge redistribution in thinner HfO2 layer results from deeper trap energies.

Metal Floating Gate Memory Device With SiO2/HfO2 Dual-Layer as Engineered Tunneling Barrier

Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2× nm. In this letter, it is demonstrated that stacked metal FG memory cell with SiO2/HfO2 dual-layer engineered tunneling barrier shows good memory characteristics. It presents favorable performance with lower operation voltage as well as enhanced program/erase speed. Furthermore, improvement of data retention is also obtained, proving that SiO2/HfO2 engineered tunnel barrier is promising for the improvement of metal FG memory performance.

Low temperature atomic layer deposited HfO2 film for high performance charge trapping flash memory application

The impact of key process parameters on the electrical characteristics of atomic layer deposited HfO2 films has been systematically studied with MHOS devices via capacitance–voltage (C–V) measurement. C–V hysteresis curves revealed that charge storage capacity is significantly enhanced with decreasing substrate temperature from 350 down to 150 °C and/or increasing purge time of the inert gas. The developed HfO2 trapping layer was also demonstrated by a MAHOS memory device. Improved memory window, fast program speed and good retention characteristics have been obtained. The study provides a reference for memory performance improvement of HfO2-based charge trap flash memory.

Visualization on charge distribution behavior in thickness-scalable HfO 2 trapping layer by in-situ electron holography and Kelvin Probe Force Microscopy technology

In this paper, charge transportation and storage characteristics of HfO2 charge-trapping layer with various thicknesses were systematically investigated for three dimension (3D) memory device application. For the first time, charge transportation behavior is visualized by introducing in-situ electron holography technology. Under programming transient state mode, charge distribution near blocking oxide is clearly observed followed by lateral charge spreading through HfO2 grain boundary. Meanwhile, steady state behaviors are also given by Kelvin Probe Force Microscopy technique. With HfO2 trapping layer is scaled from 10nm into 3nm, although enough charge storage capability guaranteed mainly by Interface trap sites, severe degradation in data retention characteristics becomes bottleneck. Also, it is proved that the interfaces provide dominate trap sites and vertical decay plays a superior role in charge loss. Finally, nano-scale effects of HfO2 trapping layer are demonstrated from experiment which is well agreed with our characterization results. The study may provide optimization for charge trapping structures, especially for high-density 3D NAND flash applications.

Temperature dependence of electron transport on a bound-to-continuum terahertz quantum cascade laser

We investigate the temperature effects on electron transport in a bound-to-continuum terahertz quantum cascade laser using Monte Carlo simulation which includes electron–electron and electron–phonon scattering. The effects of carrier transport paths and mechanisms, especially for those related to laser levels, on the devices temperature performance are evaluated. The simulation shows that the parasitic leakage of carriers from the upper laser level and the thermal backfilling to the lower laser level is the main limiting factor for high-temperature operation. The calculations are in good agreement with experimental results.

Correction to "Investigation of charge loss mechanism of thickness-scalable trapping layer by variable temperature Kelvin probe force microscopy" [Jul 13 870-872]

In the above-named article [ibid., vol. 34, no. 7, pp. 870-872, Jul. 2013], the corresponding author is not correctly indicated. Z. Huo and M. Liu should be the authors to whom correspondence for the published letter should be directed toward.

Effect of Pre-annealing to Blocking Oxide on the Performance of Dual Trapping-layer Engineered Charge Trapping Memory

The effect of pre-annealing to blocking oxide on the performance of trapping layer engineered charge trapping flash memory was investigated in this work. Compared to the devices fabricated by conventional process, the devices with pre-annealing treatment exhibit larger memory window, faster program speed, and significantly improved data retention. The enhancement of memory performance and reliability can be possible from the improvement of blocking oxide quality and the change of band-gap and band offsets in memory gate stack. The findings provide a useful guide for CTM process optimization.

Numerical simulation of extraction barrier width effects on terahertz quantum cascade laser

The effect of extraction barrier width on a resonant-phonon terahertz quantum cascade laser is studied using the Monte Carlo method. The width of extraction barrier is varied from 48 to 33 Aring. The calculated threshold current density increases monotonously with decreasing extraction barrier width, while the peak gain shows nontrivial behavior. The simulation results suggest an optimum extraction barrier width of 36 Aring for peak gain.