Lei Jin

Metal Floating Gate Memory Device With SiO2/HfO2 Dual-Layer as Engineered Tunneling Barrier

Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2× nm. In this letter, it is demonstrated that stacked metal FG memory cell with SiO2/HfO2 dual-layer engineered tunneling barrier shows good memory characteristics. It presents favorable performance with lower operation voltage as well as enhanced program/erase speed. Furthermore, improvement of data retention is also obtained, proving that SiO2/HfO2 engineered tunnel barrier is promising for the improvement of metal FG memory performance.

Low temperature atomic layer deposited HfO2 film for high performance charge trapping flash memory application

The impact of key process parameters on the electrical characteristics of atomic layer deposited HfO2 films has been systematically studied with MHOS devices via capacitance–voltage (C–V) measurement. C–V hysteresis curves revealed that charge storage capacity is significantly enhanced with decreasing substrate temperature from 350 down to 150 °C and/or increasing purge time of the inert gas. The developed HfO2 trapping layer was also demonstrated by a MAHOS memory device. Improved memory window, fast program speed and good retention characteristics have been obtained. The study provides a reference for memory performance improvement of HfO2-based charge trap flash memory.

Investigation of charge loss mechanisms IN 3D TANOS cylindrical junction-less charge trapping memory

This paper presents a detailed simulation analysis of the charge loss mechanisms in 3D TANOS cylindrical junction-less charge trapping memory devices. For the programmed state, the role of tunneling through the bottom oxide and top oxide in vertical charge loss were compared, and the latter is found to be the dominant component. It is also found that lateral charge migration shows dependence on the shape of charge trapping layer. And the winding charge trapping layer shows favorable lateral migration performance. Simulation results show that lateral charge migration is more severe rather than vertical charge loss and must be focused with decreasing memory cell size. The result will give an guidance for high density 3D memory design optimization.

A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory

A new read scheme is proposed to suppress read disturbance in unselected strings of three-dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppressed effectively by about 95%. Meanwhile, boosted channel potential during read operation has been preserved to improve soft programming read disturbance by more than 85% in non-adjacent unselected memory cells, owing to the reduced electric field across tunnel oxide. Compared with the conventional scheme, the proposed scheme leads to a significant improvement in read disturbance characteristics with a shorter read period as well as a simplified waveform of read operation.

Gate Bias Dependence of Complex Random Telegraph Noise Behavior in 65-nm NOR Flash Memory

The dependence of complex random telegraph noise (RTN) behavior on gate bias is investigated. Noise-type transition among 1/f noise, two-level RTN, and three-level RTN is observed depending on the gate bias. The transition can be detected in both program and erase states and the corresponding transition voltage decreases with the increase of threshold voltage. The phenomena are interpreted by the spectroscopic analysis of process-induced trap and stress-induced trap. A three regions model is finally proposed.

The Optimization of Gate All Around-L-Shaped Bottom Select Transistor in 3D NAND Flash Memory

In this work, the GAA (Gate All Around) L-Shaped bottom select transistor (BSG) in 3D NAND Flash Memory has been investigated. Different methods are proposed to optimize its performance from viewpoints of process and structure. BSG in 3D NAND is a novel device structure with two connected transistors: one is horizontal MOSFET (regarded as convention MOSFET) and one is vertical MOSFET (regarded as GAA transistor). With implant dose increasing in vertical channel, BSG Vth has much more tighter Vt distribution, which is beneficial for boosting potential improvement and program disturbance suppression. Meanwhile, BSG corner rounding is proposed to improve the characteristic of BSG. Experiment and TCAD simulation data are matches quite well, giving a way to improve cell characteristics distribution and self-boosting potential control in high density 3D NAND array.

Impact of critical geometry dimension on channel boosting potential in 3D NAND memory

The impact of polysilicon thickness (THK-poly) and channel hole diameter (CHCD) on channel boosting potential during program inhibit has been studied with Sentaurus device simulator for three dimensional (3D) NAND memory. According to the distribution of boosting potential along the channel, the potential level of thinner THK-poly is higher than that of thicker one. Moreover, the correlation between boosting potential and CHCD also depends on the THK-poly. In the case of 20nm THK-poly, strong dependence between potential and CHCD is observed. When the THK-poly decreases to 5nm, boosting potential is almost independent with the CHCD. Our results provide guidance for predicting and optimizing the program disturbance characteristic for highly reliable 3D NAND flash memory.

String select transistor leakage suppression by threshold voltage modulation in 3D NAND Flash Memory

Single drain select transistor (DSL) in 3D Flash memory may exhibit higher leakage as compared with DSL in 2D NAND, because of worse subthreshold swing characteristics due to poly-Si channel. Select transistor leakage suppression is essential in 3D NAND Flash Memory, in consideration of boosting potential and program disturbance. Compared to single Si drain select transistor in 2D planner Flash Memory, a novel dual cylindrical thin film transistor is proposed as drain select device to suppress leakage for good boosting performance in 3D NAND flash. And a novel measurement approach is also proposed to quantify leakage of drain select transistor in program inhibit case. The effect of Vth modulation on leakage is evaluated with this new DSL approach in this work. Single poly-Si cylindrical transistors demonstrated to be not applicable in 3D NAND because of high leakage. And the optimized Vth modulation pattern of dual transistors, with lower T1 Vth and higher T2 Vth has been found for good leakage suppression, which is beneficial for self-boosting performance of 3D NAND cell string.

Simulation on threshold voltage of L-shaped bottom select transistor in 3D NAND flash memory

A comprehensive simulation analysis method is proposed to improve the bottom select gate (BSG) transistors Vth distribution by adopting under-channel implant in this work.

Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory

ABSTRACT Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2X nm. In this work, metal FG memory device with high-k engineered Inter-Gate-Dielectric (IGD) and/or tunneling layer (TL) was detailed investigated. It presents improved performance with lower operation voltage as well as faster speed, compared to control samples. Furthermore, improvement of long-term data retention is observed for the high-k engineered devices, proving that the introduction of engineered IGD and/or TL is a promising solution for further performance improvement of full metal FG memory device.