Zongliang Huo

Controllable Growth of Nanoscale Conductive Filaments in Solid-Electrolyte-Based ReRAM by Using a Metal Nanocrystal Covered Bottom Electrode

Resistive memory (ReRAM) based on a solid-electrolyte insulator is a promising nanoscale device and has great potentials in nonvolatile memory, analog circuits, and neuromorphic applications. The underlying resistive switching (RS) mechanism of ReRAM is suggested to be the formation and rupture of nanoscale conductive filament (CF) inside the solid-electrolyte layer. However, the random nature of the nucleation and growth of the CF makes their formation difficult to control, which is a major obstacle for ReRAM performance improvement. Here, we report a novel approach to resolve this challenge by adopting a metal nanocrystal (NC) covered bottom electrode (BE) to replace the conventional ReRAM BE. As a demonstration vehicle, a Ag/ZrO(2)/Cu NC/Pt structure is prepared and the Cu NC covered Pt BE can control CF nucleation and growth to provide superior uniformity of RS properties. The controllable growth of nanoscale CF bridges between Cu NC and Ag top electrode has been vividly observed by transmission electron microscopy (TEM). On the basis of energy-dispersive X-ray spectroscopy (EDS) and elemental mapping analyses, we further confirm that the chemical contents of the CF are mainly Ag atoms. These testing/metrology results are consistent with the simulation results of electric-field distribution, showing that the electric field will enhance and concentrate on the NC sites and control location and orientation of Ag CFs.

Performance enhancement of multilevel cell nonvolatile memory by using a bandgap engineered high-κ trapping layer

A high-κ based charge trap flash (CTF) memory structure using bandgap engineered trapping layer HfO2/Al2O3/HfO2 (HAH) has been demonstrated for multilevel cell applications. Compared to a single HfO2 trapping layer, a CTF memory device based on the HAH trapping layer exhibits a larger memory window of 9.2 V, faster program/erase speed, and significantly improved data retention. Enhancements of memory performance and reliability are attributed to the modulation of charge distribution by bandgap engineering in trapping layer. The findings provide a guide for future design of CTF.

Enhanced DNA Sequencing Performance Through Edge-Hydrogenation of Graphene Electrodes

The use of graphene electrodes with hydrogenated edges for solid-state nanopore-based DNA sequencing is proposed, and molecular dynamics simulations in conjunction with electronic transport calculations are performed to explore the potential merits of this idea. The results of the investigation show that, compared to the unhydrogenated system, edge-hydrogenated graphene electrodes facilitate the temporary formation of H-bonds with suitable atomic sites in the translocating DNA molecule. As a consequence, the average conductivity is drastically raised by about 3 orders of magnitude while exhibiting significantly reduced statistical variance. Furthermore, the effect of the distance between opposing electrodes is investigated and two regimes identified: for narrow electrode separation, the mere hindrance due to the presence of protruding hydrogen atoms in the nanopore is deemed more important, while for wider electrode separation, the formation of H-bonds becomes the dominant effect. Based on these findings, it is concluded that hydrogenation of graphene electrode edges represents a promising approach to reduce the translocation speed of DNA through the nanopore and substantially improve the accuracy of the measurement process for whole-genome sequencing.

Low-Power and Highly Uniform Switching in

In this letter, the insertion of a Cu nanocrystal (NC) layer between the Pt electrode and ZrO2 film is proposed as an effective method to improve resistive switching properties in the ZrO2-based resistive switching memory. This Cu/ZrO2:Cu/Cu NC/Pt memory exhibits asymmetric nonpolar resistive switching behavior, low operating voltage (<; 1.2 V), low Reset current (<; 50 μA), and high uniformity of resistance switching. The switching mechanism is believed to be related with the formation and rupture of conductive filament. The NC-induced electrical field enhancement has the benefit to accelerate and control the CF formation process, thus leading to low-switching threshold voltage and high uniformity.

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In this letter, the resistive random access memory (RRAM) with metal-insulator-metal structure is investigated for the first time under radiation conditions. The fabricated Cu-doped HfO₂-based RRAM devices are found to have immunity from ⁶⁰Co γ ray of various dose ranges. The basic RRAM parameters such as high-resistance state, low-resistance state, SET/RESET voltages, operation speed, and endurance have nearly no degradation after ⁶⁰Co γ ray treatment with a total dose as high as 3.6 × 10⁵ rad (Si). Furthermore, a retention characteristic of 10⁵ s is also achieved during radiation. The highly stable characteristics of Cu-doped HfO₂ -based RRAM devices under radiation provide RRAM a great potential for aerospace and nuclear applications.

-Based ReRAM With a Cu Nanocrystal Insertion Layer

A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si₃N₄/Al₂O₃/Si₃N₄ (NAN) was adopted as a trap layer in place of single Si₃N₄ layer in TANOS structure (Y. Shin et al., 2005). Compared to the reference structure of single Si₃N₄ trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (~10 V), which is ideal for multi-level application. In addition, highly reliable operation is obtained due to lower program/erase voltages, superior endurance, and smaller room/high temperature pre-/post-cycling charge loss (DeltaVth <0.5 V).

Highly Stable Radiation-Hardened Resistive-Switching Memory

Graphene exhibits unique electronic properties, and its low dimensionality, structural robustness, and high work-function make it very promising as the charge storage media for memory applications. Along with the development of miniaturized and scaled up devices, nanostructured graphene emerges as an ideal material candidate. Here we proposed a novel non-volatile charge trapping memory utilizing isolate and uniformly distributed nanographene crystals as nano-floating gate with controllable capacity and excellent uniformity. Nanographene charge trapping memory shows large memory window (4.5 V) at low operation voltage (±8 V), good retention (>10 years), chemical and thermal stability (1000°C), as well as tunable memory performance employing with different tunneling layers. The fabrication of such memory structure is compatible with existing semiconductor processing thus has promise on low-cost integrated nanoscale memory applications.

Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory

Charge-trapping memory with high-κ insulator films is a candidate for future memory devices. Many efforts with different indirect methods have been made to confirm the trapping position of the charges, but the reported results in the literatures are contrary, from the bottom to the top of the trapping layers. Here we characterize the local charge distribution in the high-κ dielectric stacks under different bias with in situ electron holography. The retrieved phase change induced by external bias strength is visualized with high spatial resolution and the negative charges aggregated on the interface between Al₂O₃ block layer and HfO₂ trapping layer are confirmed. Moreover, the positive charges are discovered near the interface between HfO₂ and SiO₂ films, which may have an impact on the performance of the charge-trapping memory but were neglected in previous models and theory.

Isolated nanographene crystals for nano-floating gate in charge trapping memory

Different from conventional unipolar-type 1D-1R RRAM devices, a bipolar-type 1D-1R memory device concept is proposed and successfully demonstrated by the integration of Ni/TiOx/Ti diode and Pt/HfO2/Cu bipolar RRAM cell to suppress the undesired sneak current in a cross-point array. The bipolar 1D-1R memory device not only achieves self-compliance resistive switching characteristics by the reverse bias current of the Ni/TiOx/Ti diode, but also exhibits excellent bipolar resistive switching characteristics such as uniform switching, satisfactory data retention, and excellent scalability, which give it high potentiality for high-density integrated nonvolatile memory applications.

In situ electron holography study of charge distribution in high-κ charge-trapping memory.

The endurance of Si nanocrystal memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (V(th)) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of V(th), indicating that the generation of interface traps plays a dominant role. The charge pumping and the mid-gap voltage methods have been used to analyze endurance degradation both qualitatively and quantitatively. It is concluded that high erase voltage causes severe threshold voltage degradation by generating more interface traps and trapped oxide charges.