Yun Chiu

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.

Least mean square adaptive digital background calibration of pipelined analog-to-digital converters

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration

This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06-mm2 silicon area in a 0.13-μm CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.

A 12b 22.5/45MS/s 3.0mW 0.059mm 2 CMOS SAR ADC achieving over 90dB SFDR

CMOS technology scaling has opened a pathway to high-performance analog-to-digital conversion in the nanometer regime, where switching is preferred over amplifying. Successive-approximation-register (SAR) is one of the conversion architectures that rely on the high switching speed of process technology, and is thus distinctively known for its superior energy efficiency, small chip area, and good digital compatibility. When properly implemented, a SAR ADC also benefits from a potential rail-to-rail input swing, 100% capacitance utilization during input sampling (thus low kT/C noise), and insensitivity to comparator offsets during the conversion process. The linearity-limiting factors for SAR ADC are capacitor mismatch, sampling switch non-idealities, as well as the reference voltage settling issue due to the high internal switching speed of the DAC. In this work, a sub-radix-2 SAR ADC is presented, which employs a perturbation-based digital background calibration scheme and a dynamic-threshold-comparison (DTC) technique to overcome some of these performance-limiting factors.

Inherently linear capacitor error-averaging techniques for pipelined A/D conversion

New passive capacitor mismatch error-averaging techniques for pipelined analog-to-digital conversion is presented. The excellent linearity inherent to the architecture effectively eliminates the capacitor matching requirement that prevents a conventional monolithic pipelined analog-to-digital converter from reaching a 10-bit and above integral nonlinearity (INL) without trimming and/or calibration. Simulation results confirm the observation and a case of 14 bit INL realized by 7 bit capacitor matching is shown. The relaxed matching requirement enables the scale-down of the capacitor sizes to that of the KT/C limit. As a result, great reductions in both power consumption and chip area can be achieved.

A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation

An adaptive, digital, baseband predistortion (PD) algorithm that compensates for the memoryless nonlinearities of radio-frequency (RF) power amplifiers (PAs) for wireless systems using non-constant-envelop modulation schemes is presented. Compared with the conventional, complex-gain predistorters based on lookup tables (LUTs), the proposed direct-learning, multilevel lookup table (ML-LUT) approach assisted by a hardware-efficient loop delay compensation scheme achieves a significant reduction in convergence time and an improvement in linearization accuracy in the presence of an unknown loopback delay. The experimental results in an FPGA prototyping platform show that the fast adaptation speed enables the predistorter to track time-varying PA nonlinearities as fast as in the tens of kilohertz range, constituting a potential solution for highly efficient PAs in mobile handsets.

Scaling of analog-to-digital converters into ultra-deep-submicron CMOS

This paper presents the opportunities and challenges for scaling A/D converters into ultra-deep-submicron CMOS technologies. With faster transistors and better matching, the trend is to migrate into higher sample rates with lower resolutions. Limited dynamic range at low supply voltages remains the utmost challenge for high-resolution Nyquist converters, and oversampling will become the dominant technique in this arena in the future. Linearity correction with digital calibration is also becoming prevalent as the efficiency of calibration circuitry improves

Broad-band electronic linearizer for externally modulated analog fiber-optic links

Linearization of analog fiber-optic links using a novel CMOS linearization circuit is reported. A 17-dB suppression of the third-order intermodulation product (IMP3) has been achieved at the modulation index of 49.6 % and over a broad-band frequency range from dc to 1.3 GHz. In an experimental link with a noise floor of -124 dBm/Hz, the spurious free dynamic range (SFDR) is improved by 14 dB from 85 dB/Hz/sup 2/3/ to 99 dB/Hz/sup 2/3/.

Background ADC calibration in digital domain

A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The complete 0.13 mu ADC SoC occupies a die size of 3.7 mm times 4.7 mm, and consumes a total power of 448 mW.

SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration

A 10-b, 100-MS/s pipelined analog-to-digital converter (ADC) without dedicated front-end sample-and-hold amplifier (SHA) converts from dc to the 12th Nyquist band with in situ, mostly digital background calibration for the clock skew in the 3.5-b front-end stage. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the front-end sub-ADC to synchronize with that of the sample-and-hold (S/H) in the multiplying digital-to-analog converter (MDAC). The prototype ADC, implemented in a 90-nm CMOS process, digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled (with the default sub-ADC sample point set at the midpoint of the delay range). The prototype with calibration circuits fully integrated on chip consumes 12.2 mW and occupies 0.26-mm2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise and distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band.