Benwei Xu

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-leakage digital process. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this work to attain high conversion throughput and power savings at the same time using a simple, low-gain (~30 dB) residue amplifier. The overall architecture and the digital calibration also enable the downsizing of the first SAR stage to that of the kT/C limit, yielding a wideband input network delivering an over 80 dB spurious-free dynamic range (SFDR) while digitizing a 300 MHz input at 160 MS/s. The core ADC consumes 4.96 mW and occupies an area of 0.042 mm2; the calibration circuits dissipate 0.1 mW (estimated). An 86.9 dB SFDR and a 66.7 dB signal-to-noise plus distortion ratio (SNDR) were measured with a 2 Vpp, 5 MHz sine-wave input at full speed. The ADC achieves a Walden figure-of-merit (FoM) of 20.7 fJ/conversion-step with a Nyquist input.

A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration

A 12b two-step pipelined SAR ADC reports a 66.7dB SNDR and an 86.9dB SFDR for a 5MHz sinusoidal input at 160MS/s. A digital background calibration based on opportunistic PN injection treats both DAC mismatch and residue-amplifier gain errors. The calibration enables a significant downsizing of the ADC input capacitance to yield a wideband, highly linear input network and an over-80dB SFDR while digitizing inputs from DC to 300MHz at full speed. The conversion FoM of this ADC is 20.7fJ/step at Nyquist. The prototype occupies an active area of 0.042mm2 in a 40nm CMOS low-leakage digital process.

Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters

A dynamic path-mismatch calibration operating on direct derivative information (DDI) augments the reference-path equalization technique of that treats static mismatch errors in time-interleaved (TI) analog-to-digital converters (ADC). The approach results in a comprehensive background calibration of interleaved ADC arrays suitable for digitizing wideband inputs. The DDI of the analog input is produced by a passive high-pass filter (HPF) followed by a zero-crossing comparator, and subsequently utilized in the process to extract the dynamic mismatch profiles of the TI conversion paths, i.e., timing skew, bandwidth mismatch, etc. A zero-forcing algorithm drives the adaptive tuning procedures of the converter front-end circuits to eliminate the mismatch errors at source. The non-idealities of the DDI circuitry and their impact on the calibration performance are discussed. Behavioral simulation of an 8-bit, 20-GS/s TI-ADC reveals that signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) over 47 dB and 70 dB, respectively, can be routinely obtained for single-tone inputs from DC to Nyquist after calibration, demonstrating the efficacy of the proposed technique.

Background calibration of time-interleaved ADC using direct derivative information

A new background calibration technique for correcting timing-skew mismatch errors in time-interleaved analog-to-digital converter (ADC) is reported. In this approach, the time derivative of the input signal is directly sampled and utilized for skew calibration. Reference ADC equalization is used in tandem to correct any static mismatch errors. Behavioral simulations show 26 dB and 44 dB improvement in signal-to-noise plus distortion (SNDR) and spurious-free dynamic range (SFDR) performance, respectively.

A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS

We present a power- and area-efficient 24GS/s, 6b, 16-way time-interleaved (TI) ADC array, featuring a voltage-time (v/t) hybrid two-step structure for high-speed and low-power operation, a crosstalk-free SAR DAC topology and a non-hierarchical sampling frontend obviating reference and input buffers, respectively, for power and area savings. Background timing-skew calibration via dithering a reference ADC is also reported. Fabricated in 28nm CMOS, the prototype ADC array consumes 23mW at 24GS/s and measures an SNDR/SFDR of 35/54dB for a low-frequency input and 29/41dB for a Nyquist input, respectively. The core area of the ADC is 0.03mm2.

A 0.073-mm 2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM

An area-efficient time-domain conversion technique is reported to achieve 10-GS/s, 6-bit resolution in 65-nm CMOS. The front-end single voltage-to-time converter (VTC) running at full speed obviates any clock-skew calibration often needed in time interleaved ADCs. The inherent folding effect of the time-to-digital converter (TDC) employing ring oscillator (RO) as quantizers helps significantly to lower the back-end complexity while providing a built-in dynamic element matching (DEM) feature. Fabricated in a 65-nm CMOS process, the prototype occupies a silicon area of 0.073 mm2. The measured DNL and INL, thanks to the DEM, are +0.27/-0.28 LSBs and +0.48/-0.49 LSBs, respectively. The measured SFDR and SNDR are over 42 dB and 27 dB with a Nyquist input at 10 GS/s. The ADC achieves a FoM of 0.5 pJ/conversion-step.

28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS

High-resolution, low-power radiation-tolerant ADCs are under great demand from medical, aerospace and high-energy physics applications. In the ATLAS Liquid Argon Calorimeter of the LHC experiment at CERN, the radiation operation condition coupled with the large dynamic range (>12b ENOB), 40-80MS/s sample rate and low power (for cooling system requirement) specs [1] make the design of such ADCs a very challenging task.

A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM

An area-efficient, time-domain folding ADC achieves a 10 GS/s conversion speed and a 6 bit resolution in 65 nm CMOS. The natural time-domain folding effect of the ring oscillator (RO) leads to an inherently linear and compact folding operation. The single front-end voltage-to-time converter (VTC) running at the full conversion speed obviates any input buffer or clock-skew calibration often needed in large arrays of time-interleaved (TI) ADCs. The converter back-end consists of a four-way TI, RO-based time-to-digital converter (TDC) array with inherent dynamic element matching (DEM) that achieves high conversion speed and good linearity simultaneously. The prototype ADC was fabricated in a 65 nm CMOS process with an active area of only 0.073 mm2. Thanks to the built-in DEM, the measured DNL and INL are +0.27/-0.28 LSBs and +0.48/-0.49 LSBs, respectively. The measured SFDR and SNDR are over 42 dB and 27 dB with a Nyquist input at 10 GS/s.

A 24.7 mW 65 nm CMOS SAR-Assisted CT

A continuous-time (CT) sixth-order ΔΣ modulator, employing a 4 bit asynchronous successive-approximation-register (ASAR) quantizer, incorporates second-order noise coupling (NC) and excess-loop-delay compensation, all are tightly integrated into the switched-capacitor (SC) SAR digital-to-analog converter (DAC). The mixed-mode second-order NC structure is implemented in both discrete-time (DT) and CT domains. Clocked at 900 MHz, the 65 nm CMOS prototype measures a 120 dB/decade shaped noise slope and a peak 75.3 dB SNDR at an over-sampling ratio (OSR) of 10, yielding a Schreier FoM of 167.9 dB and a Walden FoM of 57.7 fJ/conversion-step. The modulator occupies an active area of 0.16 mm2 and consumes 24.7 mW.

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This paper presents a power- and area-efficient 16-way time-interleaved (TI) analog-to-digital converter (ADC) achieving 24-GS/s conversion speed and 6-bit resolution in 28-nm CMOS. A voltage-time hybrid pipeline technique exploiting the comparator input-voltage-output-time dependency is reported to enhance the throughput of successive-approximation-register (SAR) ADCs. A reference-buffer-free capacitive digital-to-analog (CDAC) converter is utilized to mitigate the crosstalk problem in TI-ADCs. Timing mismatches between individual sub-ADCs are estimated with a reference-ADC dithering technique and corrected by digitally controlled delay lines (DCDL). The techniques collectively enabled a very compact design, obviating any input buffer or hierarchical sampling structures. The ADC core consumes 23 mW and occupies an area of 0.03 mm2. A signal-to-noise plus distortion ratio (SNDR) of 35 dB and a spurious-free dynamic range (SFDR) of 54 dB were measured for a 40-MHz input. For a Nyquist input, the prototype measured an SNDR of 29 dB and an SFDR of 41 dB with all timing mismatch spurs suppressed below −50 dBc after skew calibration.