D. Gong

LOCx2, a low-latency, low-overhead, 2 × 5.12-Gbps transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade

In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. LOCx2 is fabricated with a commercial 0.25-μm Silicon-on-Sapphire CMOS technology and is packaged in a 100-pin QFN package. The power consumption of LOCx2 is about 843 mW.

28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS

High-resolution, low-power radiation-tolerant ADCs are under great demand from medical, aerospace and high-energy physics applications. In the ATLAS Liquid Argon Calorimeter of the LHC experiment at CERN, the radiation operation condition coupled with the large dynamic range (>12b ENOB), 40-80MS/s sample rate and low power (for cooling system requirement) specs [1] make the design of such ADCs a very challenging task.

High-speed, high-resolution, radiation-tolerant SAR ADCs for particle physics experiments

We present two CMOS 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) designs and the total dose irradiation test results of the second, a 12-bit, 160-MS/s two-step SAR ADC in 40-nm CMOS. This second SAR ADC, which measured a 67.5-dB signal-to-noise plus distortion ratio (SNDR) and a >85-dB spurious-free dynamic range (SFDR), showed minimal degradation after being exposed to a total ionizing dose (TID) of up to 1 Mrad. The measured power consumption is 4.5 mW and 6.1 mW at 80 MS/s and 160 MS/s, respectively. The small silicon area of both ADCs also exhibits a great advantage for treating single event effects (SEE) using redundancy techniques, e.g., the triple modular redundancy (TMR), with much less concern for additional area overhead in a future upgrade than designs that occupy large silicon area. The experimental results reveal great potentials of SAR ADC implemented in scaled bulk CMOS process for the front-end digitizing applications of high-energy particle physics experiments.

A linear optimal filtering approach for pileup noise removal in high-rate liquid ionization calorimeters

This paper extends the linear optimal filtering (LOF) technique to the treatment of pileup noise in high-rate liquid ionization calorimeters. A two-tuple pileup case is formulated by evaluating the χ2 function defined over a set of signal samples. A first-order (linear) approximation applied to the result readily leads to the discovery of four linear FIR filters that are capable of continuous operation and amenable to hardware realization. Monte Carlo simulation is performed to validate the proposed approach using parameters extracted from the ATLAS liquid argon calorimeter readout system. The LOF yields accurate estimation of the pulse amplitude and arrival time in presence of signal pileup. A parallel as well as an iterative configuration of the LOF are discussed and contrasted in terms of hardware efficiency and execution speed.

Status report on the LOC ASIC

Based on a commercially available 0.25 μm Silicon on Sapphire CMOS technology, we are developing the LOC ASIC for high speed serial data transmission in the front-end electronics systems of the ATLAS upgrade for the SLHC 1 . Evaluation of this technology for applications in the SLHC, based on a dedicated test chip, has been performed with irradiation tests in gamma (Co-60) and in 230 MeV proton beams. Test results indicate that this may be a candidate technology of ASIC developments for the SLHC. More thorough evaluation tests will be carried out under another R&D program supported through the Advanced Detector Research (ADR) from the Department of Energy. Characterization tests on the first prototype serializer, LOC1, have been carried out in lab. Based on the lessons learned from this chip, we propose a new architecture design of the second prototype, LOC2, aiming for a serial data rate in the range of 5 Gbps. Simulation on key components of LOC2 are being carried out and the results we have so far are presented in this note. LOC2 is scheduled to be submitted for fabrication in the first half of 2009.

Developments of two 4 × 10 Gb/s VCSEL array drivers in 65 nm CMOS for HEP experiments

This paper presents the designs and test results of two radiation tolerant 4 × 10 Gb/s vertical cavity surface emitting laser (VCSEL) array drivers VLAD and lpVLAD, both fabricated in a 1.2 V 65 nm CMOS technology. VLAD adopts a power efficient bandwidth-boost technology, and lpVLAD employs a novel high-efficiency output structure to achieve an ultra-low power consumption of 2.2 mW/Gb/ch with 2 mA bias current and 6 mA modulation current. Both drivers are optically tested passing 10 Gb/s eye mask with all channels active under the radiation of a total dose up to 350 Mrad(SiO2).

A low-power 12.5 Gbps serial link transmitter ASIC for particle detectors in 65 nm CMOS

This paper presents a 12.5 Gbps serial link transmitter application-specific integrated circuit (ASIC) designed in a 65-nm CMOS technology. The ASIC mainly includes an LC-VCO phase-locked-loop (PLL), a 16:1 serializer and a CML driver. Simulation results show that the PLL achieves a 7-to-14 GHz frequency tuning range and an RMS jitter of 0.4 pS. The serializer has a deterministic jitter of 9 pS and a programmable output swing from 200 mV to 1.0 V. The PLL and the serializer consumes 39.6 mW and 73 mW from a 1.2 V power supply, respectively.

A low-power 10-bit 250 MS/s dual-channel pipeline ADC in 0.18 μm CMOS

This paper presents a 10-bit 250-MS/s time-interleaved pipelined analog-to-digital data converter (ADC). A distributed clocking scheme is developed to eliminate timing skew between channels without introducing load capacitance to the driving buffer of the ADC. The channel offset and gain mismatch errors are calibrated in digital domain. In addition, a switch-embedded opamp-sharing technique is developed to reduce the ADC power consumption and eliminate the memory effect. The simulated SNDR and SFDR are 61.84 dB and 78.2 dB, respectively. The ADC core consumes 28 mW under a 1.8 V supply at 250 MS/s sampling rate.

A 12-bit 60-MS/s 36-mW SHA-less opamp-sharing pipeline ADC in 130 nm CMOS

This paper presents a 12-bit 60-MS/s SHA-less opamp-sharing pipeline analog-to-digital converter (ADC) implemented in a 0.13-μ m CMOS technology. A switch-embedded dual-input current-reused operational transconductance amplifier (OTA) with an overlapping two-phase clocking scheme is proposed to achieve low power consumption and eliminate the non-resetting and memory effects observed in conventional opamp-sharing techniques. To further reduce the power consumption, the ADC also incorporates a SHA-less multi-bit structure. The ADC achieves a signal-to-noise and distortion ratio of 64.9 dB and a spurious-free dynamic range of 77.1 dB at 60 MS/s. It occupies 2.3 mm 2 of area and consumes 36 mW of power under a 1.2-V supply.

On the performance of linear optimal filter and Wiener filter for signal detection in liquid ionization calorimeters

The performance of the linear optimal filter (LOF) is compared to the newly reported Wiener filter for signal detection in ATLAS liquid ionization calorimeters. The equivalence between the two methods is established, and further related to the conventional notion of (whitening + matched) filter configuration for optimal signal detection in presence of colored noise. Without arrival time spread, the LOF and Wiener results converge to each other, regardless of the SNR of the calorimeter readout path. In addition, the LOF performance displays a dependence on the pulse arrival time delay-manifested as a non-zero mean and an elevated standard deviation of the amplitude estimation error-due to the truncation of high-order terms in deriving the linear filter. In contrast, once trained with the exact signal statistics of the calorimeter, i.e., the arrival time spread and noise structure, the Wiener filter can always adapt to an optimal, unbiased solution using the same linear FIR filter structure. However, when such prior knowledge is removed, the Wiener outcomes nearly coincide with those of the LOF. All the results are obtained via Monte Carlo simulations of a readout signal-processing chain assuming identical electrical parameters of the ATLAS liquid argon calorimeter system with a sample rate of 80 MSPS. The equivalence between the two approaches is also examined and confirmed using a Gaussian pulse shape and an invertible pulse-shaping function without any finite zeroes on the jω-axis.